Using Data-Bus Write-Only; Figure 8-25. Ieee 1149.1A-1993 Compliant Boundary-Scan Interface; Figure 8-26. Data-Bus Write-Only Transaction - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

Figure 8-25. IEEE 1149.1a-1993 Compliant Boundary-Scan Interface

8.9 Using Data-Bus Write-Only

The 750GX supports split-transaction pipelined transactions. It supports a limited out-of-order capability for its
own pipelined transactions through the data-bus write-only (DBWO) signal. When recognized on the clock of
a qualified DBG, the assertion of DBWO directs the 750GX to perform the next pending data write tenure (if
any), even if a pending read tenure would have normally been performed because of address pipelining. The
DBWO signal does not change the order of write tenures with respect to other write tenures from the same
750GX. It only allows a write tenure to be performed ahead of a pending read tenure from the same 750GX.
In general, an address tenure on the bus is followed strictly in order by its associated data tenure. Transac-
tions pipelined by the 750GX complete strictly in order. However, the 750GX can run bus transactions out of
order only when the external system allows the 750GX to perform a cache-line-snoop-push-out operation (or
other write transaction, if pending in the 750GX write queues) between the address and data tenures of a
read operation through the use of DBWO. This effectively envelopes the write operation within the read oper-
ation. Figure 8-26 shows how the DBWO signal is used to perform an enveloped write transaction.

Figure 8-26. Data-Bus Write-Only Transaction

Read Address
(1)
BG
ABB
AACK
Bus Interface Operation
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TDI (Test Data Input)
TMS (Test Mode Select)
TCK (Test Clock Input)
TDO (Test Data Output)
TRST (Test Reset)
Write Address
(2)
Write Data
(2)
DBG
DBB
DBWO
Enveloped Write
Transaction
Read Data
(1)
gx_08.fm.(1.2)
March 27, 2006