IBM PowerPC 750GX User Manual page 367

NaN not a number
no-op no operation
OEA operating environment architecture
PID processor identification tag
PLL phase-locked loop
PLRU pseudo least recently used
PMCn Performance-Monitor Counter Registers
POR power-on reset
POWER Performance Optimized with Enhanced RISC architecture
PTE page table entry
PTEG page-table-entry group
PVR Processor Version Register
RAW read-after-write
RISC reduced instruction set computing
RTL register transfer language
RWITM read with intent to modify
RWNITM read with no intent to modify
SDA sampled data address register
Register that specifies the page table base address for virtual-to-physical address transla-
SDR1
tion.
SIA Sampled Instruction Address Register
SPR Special-Purpose Register
SRn Segment Register
SRR0 Machine Status Save/Restore Register 0
SRR1 Machine Status Save/Restore Register 1
SRU system register unit
TAU thermal-management assist unit
TB time-base facility
TBL Time Base Lower Register
TBU Time Base Upper Register
gx_acronyms.fm.(1.2)
March 27, 2006
IBM PowerPC 750GX and 750GL RISC Microprocessor
User's Manual
Acronyms and Abbreviations
Page 367 of 377