Special-Purpose Registers Used By Performance Monitor; Table 11-1. Performance Monitor Sprs - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
As a result of a performance-monitor exception being taken, the action taken depends on the programmable
events. To help track which part of the code was being executed when an exception was signaled, the
address of the last completed instruction during that cycle is saved in the Sampled Instruction Address (SIA)
register. The SIA is not updated if no instruction completed the cycle in which the exception was taken.
Exception handling for the Performance-Monitor Interrupt Exception is described in Section 4.5.13, Perfor-
mance-Monitor Interrupt (0x00F00), on page 172.

11.2 Special-Purpose Registers Used by Performance Monitor

The performance monitor incorporates the SPRs listed in Table 11-1. All of these supervisor-level registers
are accessed through Move-to Special Purpose Register (mtspr) and Move-from Special Purpose Register
(mfspr) instructions.

Table 11-1. Performance Monitor SPRs

SPR Number
952
953
954
955
956
957
958
936
937
938
939
940
941
942
Notes:
• The user registers (UMMCR0, UMMCR1, UPMC1, and so on) contain the same values as the nonuser registers but provide read-
only access to the Performance-Monitor Registers while in user mode. An attempt to write to a user register in either supervisor or
user mode results in a program interrupt.
• Reading and writing these registers does not synchronize the machine. An explicit synchronization instruction should be placed
before and after a Move-from Special Purpose Register (mfspr) or Move-to Special Purpose Register (mtspr) instruction to one of
these registers to ensure an accurate count.
Performance Monitor and System Related Features
Page 350 of 377
SPR[5-9] || SPR[0-4]
11101 11000
11101 11001
11101 11010
11101 11011
11101 11100
11101 11101
11101 11110
11101 01000
11101 01001
11101 01010
11101 01011
11101 01100
11101 01101
11101 01110
Register Name
MMCR0
PMC1
PMC2
SIA
MMCR1
PMC3
PMC4
UMMCR0
UPMC1
UPMC2
USIA
UMMCR1
UPMC3
UPMC4
Access Level
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
User (read only)
User (read only)
User (read only)
User (read only)
User (read only)
User (read only)
User (read only)
gx_11.fm.(1.2)
March 27, 2006