Time Base Enable (Tben)-Input; Tlb Invalidate Synchronize (Tlbisync)-Input; Processor Mode Selection Signals - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
7.2.11.4 Time Base Enable (TBEN)—Input
State Asserted
Negated
Timing Assertion/
Negation
7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)—Input
The TLB Invalidate Synchronize (TLBISYNC) signal is an input-only signal.
State Asserted
Negated
Timing Assertion/
Negation
Start-Up

7.2.12 Processor Mode Selection Signals

Table 7-6 summarizes the processor mode select signals of the 750GX. The mode select signals establish
the operating modes of the processor after reset (for example, 32-bit or 64-bit data mode or DRTRY mode).
Mode select signals are sampled at the rising transition of HRESET.
Table 7-6. Summary of Mode Select Signals
Pin
DRTRY Selects DRTRY mode.
QACK selects normal or full cycle precharge
QACK
on ABB, DBB, and ARTRY.
TLBISYNC TLBISYNC selects 32-bit or 64-bit bus mode.
Factory usage mode only. Must be tied high at
DBWO
HRESET transition.
Factory usage mode only. Must be tied high at
DBDIS
HRESET transition.
Factory usage mode only. Must be tied high at
L2_TSTCLK
HRESET transition.
Signal Descriptions
Page 274 of 377
Indicates that the time base and decrementer should continue clocking. This
signal is essentially a "count enable" control for the time base and decre-
menter counter.
Indicates that the time base and decrementer should stop clocking.
May occur on any cycle. The sampling of this signal is synchronous with
SYSCLK.
Prevents execution of a tlbsync instruction from completing.
Enables execution of a tlbsync to complete.
Might occur on any cycle.
See Table 7-6, Summary of Mode Select Signals, on page 274 for a descrip-
tion of the start-up function.
Description
Pin state at HRESET transition
'0'
No-DRTRY mode
Full cycle precharge
32-bit mode
N/A
N/A
N/A
'1'
DRTRY mode
Normal precharge
64-bit mode
Required
Required
Required
gx_07.fm.(1.2)
March 27, 2006