Cmos Signal Input/Output Group And Tap Signal Group Dc Specifications; Open Drain Output Signal Group Dc Specifications - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

Notes:
1. The V
CC_MIN
overshoot specifications.
2. Refer to
3. Refer to
4. The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Table 2-14. AGTL+ Signal Group DC Specifications
Symbol
V
IL
V
IH
V
OH
R
ON
I
LI
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
IL
value.
3. V is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
IH
value.
4. V and V
IH
signal quality specifications.
5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
Measured at 0.31*V
6. GTLREF should be generated from V
specifications is the instantaneous V
7. Specified when on-die R
Table 2-15. CMOS Signal Input/Output Group and TAP Signal Group
DC Specifications
Symbol
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
I
LI
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
TT
3. Refer to the processor I/O Buffer Models for I/V characteristics.
4. Measured at 0.1*V
5. Measured at 0.9*V
6. For Vin between 0 V and V
Table 2-16. Open Drain Output Signal Group DC Specifications
Symbol
V
OL
V
OH
I
OL
I
LO
34
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
and V loadlines represent static and transient limits. Please see
CC_MAX
Table 2-12 for processor VID information.
Table 2-13 for V Static and Transient Tolerance
CC
Parameter
Input Low Voltage
Input High Voltage GTLREF+0.10
Output High Voltage
Buffer On Resistance
Input Leakage Current
may experience excursions above V
OH
. R (min) = 0.158*R
TT ON
TT
TT
and R are turned off. V
TT ON
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
referred to in these specifications refers to instantaneous V
.
TT
.
TT
. Measured when the driver is tristated.
TT
Parameter
Output Low Voltage
Output High Voltage 0.95 * V
Output Low Current
Leakage Current
Min Typ
-0.10 0 GTLREF-0.10
V
TT
V -0.10 N/A
TT
8.25 10.25
N/A N/A
. However, input signal drivers must comply with the
TT
. R (typ) = 0.167*R
TT ON
with a 1% tolerance resistor divider. The V
.
between 0 and V
IN
Min Typ
-0.10 0.00
0.7 * V V
TT TT
-0.10 0
0.9 * V V
TT TT
1.70 N/A
1.70 N/A
N/A N/A
Min Typ
0 N/A 0.20 * V
V 1.05 * V
TT TT
16 N/A
N/A N/A
Section 2.13.2
Max Units
V
V +0.10 V
TT
V V
TT
12.25 Ω
μA
± 100
. R (max) = 0.175*R .
TT ON TT
referred to in these
TT
.
TT
Max Units
0.3 * V V
TT
V + 0.1 V
TT
0.1 * V V
TT
V + 0.1 V
TT
4.70 mA
4.70 mA
± 100 μA
.
TT
Max Units
V
TT
V
TT
50 mA
± 200 μA
for VCC
1
Notes
2,4,6
3,6
4,6
5
7
Notes 1
2,3
2
2
2
4
5
6
Notes 1
3
2
4