Video Input Port Register Descriptions; Table 6-75. Standard Geodelink™ Device Msrs Summary; Table 6-76. Vip Configuration/Control Registers Summary - AMD Geode LX 600@0.7W Data Book

33234H
6.10

Video Input Port Register Descriptions

The registers associated with the VIP are the Standard
GeodeLink Device (GLD) MSRs (accessed via the RDMSR
and WRMSR instructions) and VIP Configuration/Control
Registers. Table 6-75 and Table 6-76 are register summary
Table 6-75. Standard GeodeLink™ Device MSRs Summary
MSR Address Type
54002000h RO
54002001h R/W
54002002h R/W
54002003h R/W
54002004h R/W
54002005h R/W
VIP Memory
Offset Type
00h R/W
04h R/W
08h R/W
0Ch R/W
10h R/W
14h R/W
18h R/W
1Ch R/W
20h R/W
24h R/W
28h R/W
2Ch R/W
30h R/W
34h R/W
38h R/W
3Ch R/W
40h R/W
482
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management Register
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)

Table 6-76. VIP Configuration/Control Registers Summary

Register Name
VIP Control Register 1 (VIP_CTL_REG1)
VIP Control Register 2 (VIP_CTL_REG2)
VIP Status (VIP_STATUS)
VIP Interrupt (VIP_INT)
VIP Current/Target (VIP_CUR_TAR)
VIP Max Address (VIP_MAX_ADDR)
VIP Task A Video Even Base Address
(VIP_TASK_A_VID_EVEN_BASE)
VIP Task A Video Odd Base Address
(VIP_TASK_A_VID_ODD_BASE)
VIP Task A VBI Even Base Address
(VIP_TASK_A_VBI_EVEN_BASE)
VIP Task A VBI Odd Base Address
(VIP_TASK_A_VBI_ODD_BASE)
VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH)
VIP Control Register 3 (VIP_CONTRL_REG3)
VIP Task A V Offset (VIP_TASK_A_V_OFFSET)
VIP Task A U Offset (VIP_TASK_A_U_OFFSET)
VIP Task B Video Even Base/Horizontal End
(VIP_TASK_B_VID_EVEN_BASE_HORIZ_END)
VIP Task B Video Odd Base/Horizontal Start
(VIP_TASK_B_VID_ODD_BASE_HORIZ_START)
VIP Task B VBI Even Base/VBI End
(VIP_TASK_B_VBI_EVEN_BASE_VBI_END)
Video Input Port Register Descriptions
tables that include reset values and page references where
the bit descriptions are provided.
Note: The MSR address is derived from the perspective
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 for more details on MSR addressing.
Reset Value
00000000_ 0003C4xxh
000000000_ 00000000h
000000000_ xxxx7FFFh
000000000_ 00000000h
000000000_ 00000005h
000000000_ 00000000h
Reset Value
42000001h
00000000h
xxxxxxxxh
xxxxFFFEh
00000000h
FFFFFFFFh
00000000h
00000000h
00000000h
00000000h
00000000h
00000020h
00000000h
00000000h
00000000h
00000000h
00000000h
AMD Geode™ LX Processors Data Book
Reference
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