Table 6-66. Panel Output Signal Mapping - AMD Geode LX 600@0.7W Data Book

Processors
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33234H
6.7.7.3
FP Functional Description
The FP connects to the RGB port of the video mixer.
LCD Interface
The FP interfaces directly to industry standard 18-bit or 24-
bit active matrix thin-film-transistor (TFT). The digital RGB
or video data that is supplied by the video logic is con-
verted into a suitable format to drive a wide variety range of
panels with variable bits. The LCD interface includes dith-
ering logic to increase the apparent number of colors dis-
played for use on panels with less than 6 bits per color. The
LCD interface also supports automatic power sequence of
panel power supplies.
Pin Name
DRGB0
DRGB1
DRGB2
DRGB3
DRGB4
DRGB5
DRGB6
DRGB7
DRGB8
DRGB9
DRGB10
DRGB11
DRGB12
DRGB13
DRGB14
DRGB15
DRGB16
DRGB17
DRGB18
DRGB19
DRGB20
DRGB21
DRGB22
DRGB23
406

Table 6-66. Panel Output Signal Mapping

TFT
TFT
9-Bit
18-Bit
B0
B1
B2
B0
B3
B1
B4
B2
B5
G0
G1
G2
G0
G3
G1
G4
G2
G5
R0
R1
R2
R0
R3
R1
R4
R2
R5
Mode Selection
The FP can be configured for operation with most standard
TFT panels:
• Supports TFT panels with up to 24-bit interface with
640x480, 800x600, 1024x768, 1280x1024, and
1600x1200 pixel resolutions. Either one or two pixels per
clock is supported for all resolutions. Other resolutions
below 640x480 are also supported.
Table 6-66 shows the mapping of the data in the supported
modes.
For TFT panel support, the output from the dither block is
directly fed on to the panel data pins (DRGBx). The data
that is being sent on to the panel data pins is in sync with
the TFT timing signals such as HSYNC, VSYNC, and LDE.
One pixel (or two pixels in 2 pix/clk mode) is shifted on
every positive edge of the clock as long as DISP_ENA is
active.
TFT
24-Bit
9+9-Bit
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
AMD Geode™ LX Processors Data Book
Video Processor
TFT
TFT
12+12-Bit
BB0
BB0
BB1
BB1
BB2
BB2
BB3
GB0
GB0
GB1
GB1
GB2
GB2
GB3
RB0
RB0
RB1
RB1
RB2
RB2
RB3
BA0
BA0
BA1
BA1
BA2
BA2
BA3
GA0
GA0
GA1
GA1
GA2
GA2
GA3
RA0
RA0
RA1
RA1
RA2
RA2
RA3

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