Figure 7-4. Power Up Sequencing; Figure 7-5. Drive Level And Measurement Points For Switching Characteristics; Table 7-9. Pci Interface Signals - AMD Geode LX 600@0.7W Data Book

Electrical Specifications
V
CORE
V ,V
IO MEM
MVREF
SYSREF
RESET#
Outputs
Symbol Parameter
t Input Setup time to SYSREF
SU1
(AD[31:0], DEVSEL#,GNT[2:0]#, IRDY#, PAR,
STOP#, TRDY#)
t REQ[2:0]# Input Setup time to SYSREF
SU2
t Input Hold time from SYSREF for all PCI inputs
H
(STOP#)
(DEVSEL#, FRAME#, GNT[2:0#, IRDY#, PAR,
TRDY#, REQ[2:0]#, STOP#)
t Bused signals Valid Delay time from SYSREF
VAL1
(AD[31:0])
t GNT[2:0]# Valid Delay time from SYSREF
VAL2
Note 1. The GNT[2:0]#, IRQ13, SUSPA#, PW0, and PW1 signals are only inputs during RESET# active. They must be sta-
ble between five and two PCI clocks before RESET# inactive.
Note 2. Output delay includes tristate-to-valid transitions and valid-to-tristate timing.
SYSREF
Outputs
Inputs

Figure 7-5. Drive Level and Measurement Points for Switching Characteristics

AMD Geode™ LX Processors Data Book
t
ON
t
MVON

Figure 7-4. Power Up Sequencing

Table 7-9. PCI Interface Signals

t Min
VAL1,2
Valid Output
n
t
SU1,2
t
RSTX
t
Z
Min Max
3.0
4.5
0
2.0 6.0
2.0 5.5
t Max
VAL1,2
Valid Output
n+1
t
H1,2
Valid Input
33234H
SYSREF
cycle time not
to scale with
other delays
in this figure.
Unit Comments
ns
ns
ns Note 1
ns Note 2
ns Note 2
50%
50%
50%
609