Table 6-42. Programming Image Sizes - AMD Geode LX 600@0.7W Data Book

Display Controller
6.5.9 Interlaced Modes
For interlaced modes, the V_ACTIVE and V_TOTAL fields
are configured for the odd field. The Even Field Vertical
Timing registers (DC Memory Offsets 0E4h-0ECh) are
configured for the corresponding even field. Figure 6-22 on
page 298 shows a representative timing diagram for the
odd and even timing register settings in interlaced modes,
and Table 6-43 on page 298 presents the (decimal) timing
values for some common interlaced modes.
The DC is capable of producing an interlaced output using
any of three separate mechanisms. It can fetch the graph-
ics data in an interlaced manner, flicker filter the graphics
data, or use the same graphics data for both odd and even
Pre-scale
Horizontal
Mode Width
Default (no VGA, scal- H_ACTIVE
ing, interlacing, or flicker
filter)
Scaling only FB_H_ACTIVE
Interlacing only (no flicker H_ACTIVE
filter)
Interlacing with flicker fil- H_ACTIVE
ter
Interlacing with inter- H_ACTIVE
laced addressing (no
flicker filter)
Interlacing with scaler (no FB_H_ACTIVE
flicker filter, no interlaced
addressing)
Interlacing with scaler FB_H_ACTIVE
and flicker filter
VGA (no scaling, interlac- VGA CRTC
ing, or flicker filter)
VGA with scaling (no VGA CRTC
interlacing or flicker filter
VGA with scaling and VGA CRTC
interlacing (no flicker fil-
ter)
VGA with scaling, inter- VGA CRTC
lacing, and flicker filter
Note 1. Because the register value represents the image size minus 1, an additional 1 is added when these two register values are added
together to retain the convention.
AMD Geode™ LX Processors Data Book
fields, (which would effectively line-double the resulting
image). When the VGA is being used, interlaced address-
ing is not supported, and scaling must be used. When the
frame buffer source image or the output image is wider
than 1024 active pixels, the flicker filter is not supported.
When scaling and/or interleaving is enabled, the size of the
frame buffer image (in pixels) will vary from the size of the
output image. Table 6-42 and Table 6-44 on page 299 indi-
cates how the DC's timing register fields should be pro-
grammed for supported scaling and interlacing modes.
(Note that for VGA modes, there are several VGA registers
that can affect the size of the frame buffer image. These
registers are not enumerated in the table.)

Table 6-42. Programming Image Sizes

Pre-scale Post-scaler
Height Width
V_ACTIVE H_ACTIVE
FB_V_ACTIVE H_ACTIVE
V_ACTIVE or H_ACTIVE
V_ACTIVE_EVE
N (alternating)
V_ACTIVE + H_ACTIVE
V_ACTIVE_EVE
N + 1 (Note 1)
V_ACTIVE or H_ACTIVE
V_ACTIVE_EVE
N (alternating)
FB_V_ACTIVE H_ACTIVE
FB_V_ACTIVE H_ACTIVE
VGA CRTC VGA CRTC
VGA CRTC H_ACTIVE
VGA CRTC H_ACTIVE
VGA CRTC H_ACTIVE
33234H
Post-scaler Final (Output)
Height Width
V_ACTIVE H_ACTIVE
V_ACTIVE H_ACTIVE
V_ACTIVE or H_ACTIVE
V_ACTIVE_EVE
N (alternating)
V_ACTIVE + H_ACTIVE
V_ACTIVE_EVE
N + 11
V_ACTIVE or H_ACTIVE
V_ACTIVE_EVE
N (alternating)
V_ACTIVE or H_ACTIVE
V_ACTIVE_EVE
N (alternating)
V_ACTIVE + H_ACTIVE
V_ACTIVE_EVE
N + 11
VGA CRTC VGA CRTC
V_ACTIVE H_ACTIVE
V_ACTIVE or H_ACTIVE
V_ACTIVE_EVE
N (alternating)
V_ACTIVE + H_ACTIVE
V_ACTIVE_EVE
N + 11
Final (Output)
Height
V_ACTIVE
V_ACTIVE
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
VGA CRTC
V_ACTIVE
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
V_ACTIVE or
V_ACTIVE_EVE
N (alternating)
297