Table 6-58. Video Dac Registers Summary - AMD Geode LX 600@0.7W Data Book

33234H
6.6.21.7 Color Select
Index 14h
Type R/W
Reset Value xxh
Bit Name
7:4 RSVD
3:2 P[7:6]
1:0 P[5:4]
6.6.22 Video DAC Registers
Video DAC palette registers are accessed by writing the Palette Address register at the read or write address, then perform-
ing three reads or writes, one for each of the red, green, and blue color values. The video DAC provides an address incre-
ment feature that allows multiple sets of color triplets to be read or written without writing the Palette Address register again.
To invoke this feature, simply follow the first triplet read/write with the next triplet read/write.
The original IBM video DAC behavior for read operations is:
1) CPU initiates a palette read by writing INDEX to I/O address 3C7h.
2) Video DAC loads a temporary register with the value stored at palette[INDEX].
3) Video DAC increments INDEX (INDEX = INDEX + 1).
4) CPU reads red, green, blue color values from temporary register at I/O address 3C9h.
5) Loop to step 2.
The original IBM video DAC behavior for write operations is:
1) CPU initiates a palette write by writing INDEX to I/O address 3C8h.
2) CPU writes red, green, blue color values to temporary DAC registers at I/O address 3C9h.
3) Video DAC stores the temporary register contents in palette[INDEX].
4) Video DAC increments INDEX (INDEX = INDEX + 1).
5) Loop to step 2.
I/O
Address Type
3C8h RO
3C7h RO
3C7h RO
3C9h R/W
3C6h R/W
382
Color Select Register Bit Descriptions
Description
Reserved.
P7 and P6. These bits are used to provide the upper two bits of the 8-bit pixel value sent
to the video DAC in all modes except the 256 color mode (mode 13h).
P5 and P4. These bits are used to provide bits 5 and 4 of the 8-bit pixel value sent to the
video DAC when the P5:4 Select bit is set in the Attribute Mode Control register (Index
10h[7]). In this case, they replace bits [5:4] coming from the EGA palette.

Table 6-58. Video DAC Registers Summary

Register
Palette Address (Write Mode)
Palette Address (Read Mode)
DAC State
Palette Data
Pel Mask
Display Controller Register Descriptions
Reset Value Reference
00h Page 383
00h Page 383
00h Page 383
00h Page 380
00h Page 380
AMD Geode™ LX Processors Data Book