Code
Beeps
POST Routine Description
30h
1-4-1-1
RAM failure on data bits xxxx of high byte of memory bus
32h
Test CPU bus-clock frequency
33h
Initialize Phoenix Dispatch Manager
36h
Warm start shut down
38h
Shadow system BIOS ROM
3Ah
Autosize cache
3Ch
Advanced configuration of chipset registers
3Dh
Load alternate registers with CMOS values
42h
Initialize interrupt vectors
45h
POST device initialization
46h
2-1-2-3
Check ROM copyright notice
48h
Check video configuration against CMOS
49h
Initialize PCI bus and devices
4Ah
Initialize all video adapters in system
4Bh
QuietBoot start (optional)
4Ch
Shadow video BIOS ROM
4Eh
Display BIOS copyright notice
50h
Display CPU type and speed
51h
Initialize EISA board
52h
Test keyboard
54h
Set key click if enabled
58h
2-2-3-1
Test for unexpected interrupts
59h
Initialize POST display service
5Ah
Display prompt "Press F2 to enter SETUP"
5Bh
Disable CPU cache
5Ch
Test RAM between 512 and 640 KB
60h
Test extended memory
62h
Test extended memory address lines
64h
Jump to User Patch1
66h
Configure advanced cache registers
67h
Initialize Multi Processor APIC
68h
Enable external and CPU caches
69h
Setup System Management Mode (SMM) area
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