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Intel® Entry Server Board SE7221BA1-E TPS
IRQ
System Resource
NMI
I/O channel check
0
Reserved, interval timer
1
Reserved, keyboard buffer full
2
Reserved, cascade interrupt from slave PIC
3
User available
4
COM1
5
LPT2 (Plug and Play option)/User available
6
Diskette drive
7
LPT1
8
Real-time clock
9
User available
10
User available
11
User available
12
Onboard mouse port (if present, else user available)
13
Reserved, math coprocessor
14
Primary IDE/Serial ATA (if present, else user available)
15
Serial ATA (if present, else user available)
(Note 2)
User available (through PIRQA)
16
(Note 2)
User available (through PIRQB)
17
(Note 2)
User available (through PIRQC)
18
(Note 2)
User available (through PIRQD)
19
(Note 2)
User available (through PIRQE)
20
(Note 2)
User available (through PIRQF)
21
(Note 2)
User available (through PIRQG)
22
(Note 2)
User available (through PIRQH)
23
Notes:
1.
Default, but can be changed to another IRQ.
2.
Available in APIC mode only.
4.6
PCI Conventional Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between
the PCI Conventional bus connectors and onboard PCI Conventional devices. The PCI
Conventional specification describes how interrupts can be shared between devices attached to
the PCI Conventional bus. In most cases, the small amount of latency added by interrupt
sharing does not affect the operation or throughput of the devices. In some special cases
where maximum performance is needed from a device, a PCI Conventional device should not
share an interrupt with other PCI Conventional devices. Use the following information to avoid
sharing an interrupt with a PCI Conventional add-in card.
PCI Conventional devices are categorized as follows to specify their interrupt grouping:
Revision 1.5
Table 9. Interrupts
(Note 1)
(Note 1)
Maps and Interrupts
25
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