Fixed I/O Map; Dma Channels; Table 6. I/O Map; Table 7. Dma Channels - Intel SE7221BA1 Technical Manual

Intel® Entry Server Board SE7221BA1-E TPS
4.2

Fixed I/O Map

Address (hex)
0000 - 00FF
0170 - 0177
01F0 - 01F7
(Note 1)
0228 - 022F
(Note 1)
0278 - 027F
(Note 1)
02E8 - 02EF
(Note 1)
02F8 - 02FF
0374 - 0377
0377, bits 6:0
0378 - 037F
03E8 - 03EF
03F0 - 03F5
03F4 – 03F7
03F8 - 03FF
04D0 - 04D1
LPTn + 400
(Note 2)
0CF8 - 0CFB
(Note 3)
0CF9
0CFC - 0CFF
FFA0 - FFA7
FFA8 - FFAF
Notes:
1. Default, but can be changed to another address range.
2. Dword access only.
3. Byte access only.
NOTE: Some additional I/O addresses are not available due to ICH6-R address aliasing. The ICH6-R
data sheet provides more information on address aliasing:
http://developer.intel.com/design/chipsets/datashts
4.3

DMA Channels

DMA Channel Number
0
1
2
3
4
5
Revision 1.5

Table 6. I/O Map

Size
256 bytes
8 bytes
8 bytes
8 bytes
8 bytes
8 bytes
8 bytes
4 bytes
7 bits
8 bytes
8 bytes
6 bytes
1 byte
8 bytes
2 bytes
8 bytes
4 bytes
1 byte
4 bytes
8 bytes
8 bytes

Table 7. DMA Channels

Data Width
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
16 bits
Description
Used by the Server Board SE7221BA1-E. Refer to the ICH6-R
data sheet for dynamic addressing information.
Secondary Parallel ATA IDE channel command block
Primary Parallel ATA IDE channel command block
LPT3
LPT2
COM4
COM2
Secondary Parallel ATA IDE channel control block
Secondary IDE channel status port
LPT1
COM3
Diskette channel
Primary Parallel ATA IDE channel control block
COM1
Edge/level triggered PIC
ECP port, LPTn base address + 400h
PCI Conventional bus configuration address register
Reset control register
PCI Conventional bus configuration data register
Primary Parallel ATA IDE bus master registers
Secondary Parallel ATA IDE bus master registers
System Resource
Open
Parallel port
Diskette drive
Parallel port (for ECP or EPP)
DMA controller
Open
Maps and Interrupts
23