Intel S1200BTS Specification page 75

Intel® Server Board S1200BT TPS
Screen Field Descriptions:
1. Processor ID
Option Values:
Help Text:
Comments:
CPUID instruction) identifying the type of processor and the stepping Processor
Frequency
Option Values:
Help Text:
Comments:
2. Microcode Revision
Option Values:
Help Text:
Comments:
processor microcode.
3. L1 Cache RAM
Option Values:
Help Text:
Comments:
L1 cache is not shared between cores, this is shown as the amount of L1 cache per
core. There are two types of L1 cache for the SandyBridge processor family, this
amount is the total of L1 Instruction Cache plus L1Data Cache for each core.
4. L2 Cache RAM
Option Values:
Help Text:
Comments:
L2 cache is not shared between cores, this is shown as the amount of L2 cache per
core.
5. L3 Cache RAM
Option Values:
Help Text:
Comments:
L3 cache is shared between all cores in a processor package, this is shown as the total
amount of L3 cache per processor package. S1200BT boards have a single processor
display. Romley boards have ―N/A‖ for the second processor if not installed.
6. Processor Version
Revision 1.0
<CPUID>
<None>
Information only. Displays the Processor Signature value (from the
<Current Processor Operating Frequency>
<None>
Information only. Displays current operating frequency of the processor.
<Microcode Revision Number>
<None>
Information only. Displays Revision Level of the currently loaded
<L1 cache size>
<None>
Information only. Displays size in KB of the processor L1 Cache. Since
<L2 cache size>
<None>
Information only. Displays size in KB of the processor L2 Cache. Since
<L3 cache size>
<None>
Information only. Displays size in MB of the processor L3 Cache. Since
Intel order number G13326-003
BIOS User Interface
63