Intel S1200BTS Specification page 142

Appendix C: POST Code Diagnostic LED Decoder
Progress Code
0x06
0x07
0x08
0x09
0x0E
0x0F
0x10
0x11
0x15
0x19
0x31
0x32
0x33
0x34
0x35
0x36
0x4F
0x60
0x61
0x62
0x63
0x68
0x69
0x6A
0x70
130
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble Lower Nibble
MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB
#7 #6 #5 #4 #3 #2 #1 #0
X X X X X O O X
X X X X X O O O
X X X X O X X X
X X X X O X X O
X X X X O O O X
X X X X O O O O
PEI Phase
X X X O X X X X
X X X O X X X O
X X X O X O X O
X X X O O X X O
X X O O X X X O
X X O O X X O X
X X O O X X O O
X X O O X O X X
X X O O X O X O
X X O O X O O X
X O X X O O O O
DXE Phase
X O O X X X X X
X O O X X X X O
X O O X X X O X
X O O X X X O O
X O O X O X X X
X O O X O X X O
X O O X O X O X
X O O O X X X X
Intel order number G13326-003
Intel® Server Board S1200BT TPS
Description
Early CPU initialization during Sec
Phase
Early South Bridge initialization
Early North Bridge initialization
End Of Sec Phase
CPU Microcode Not Found.
CPU Microcode Not Loaded.
PEI Core Starts
CPU PEI Module Starts
North Bridge PEI Module Starts
South Bridge PEI Module Starts
Memory Installed
CPU PEI Module for CPU initialization
CPU PEI Module for Cache initialization
CPU PEI Module for Boot Strap
Processor Select
CPU PEI Module for Application
Processor initialization
CPU PEI Module for CPU SMM
initialization
Dxe IPL started
DXE Core started
DXE NVRAM initialization
SB RUN initialization
Dxe CPU initialization
DXE PCI Host Bridge initialization
DXE NB initialization
DXE NB SMM initialization
DXE SB initialization
Revision 1.0