Appendix C: Post Code Diagnostic Led Decoder; Table 57. Post Progress Code Led Example; Table 58. Post Progress Codes - Intel S1200BTS Specification

Intel® Server Board S1200BT TPS

Appendix C: POST Code Diagnostic LED Decoder

During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the
back edge of the server board. To assist in troubleshooting a system hang during the POST
process, you can use the diagnostic LEDs to identify the last POST process executed.
Later in POST, the BIOS displays POST Error Codes on the video monitor in the Error Manager
display. Any POST Error Codes are automatically logged in the event log.
The Diagnostic LEDs are a set of LEDs found on the back edge of the server board. The exact
implementation may differ for some boards, but in general there are 8 Diagnostic LEDs which
form a 2 hex digit (8 bit) code read left-to-right as facing the rear of the server.
An LED which is ON represents a 1 bit value, and an LED which is OFF represents a 0 bit value.
The LED bit values are read as Most Significant Bit to the left, Least Significant Bit to the right.
In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The
LEDs are decoded as follows:
MSB
LEDs
LED #7
8h
ON
Status
1
Results
Ah

Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are
concatenated as ACh.
Progress Code
0x01
0x02
0x03
0x05
Revision 1.0

Table 57. POST Progress Code LED Example

Upper Nibble LEDs
LED #6 LED #5
4h 2h
OFF ON
0 1

Table 58. POST Progress Codes

Diagnostic LED Decoder
O = On, X=Off
Upper Nibble Lower Nibble
MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB
#7 #6 #5 #4 #3 #2 #1 #0
X X X X X X X O
X X X X X X O X
X X X X X X O O
X X X X X O X O
Intel order number G13326-003
LED #4 LED #3
1h 8h
OFF ON
0 1
Ch
SEC Phase
First POST code after CPU reset
CPU Microcode load begin
Cache As RAM initialization begin
SEC Core at Power On Begin.
Appendix C: POST Code Diagnostic LED Decoder
Lower Nibble LEDs
LED #2 LED #1
4h 2h
OFF ON
1 0
Description
LSB
LED #0
1h
OFF
0
129