Intel S1200BTS Specification page 150

Glossary
Term
Hz Hertz (1 cycle/second)
I2C Inter-Integrated Circuit Bus
®
IA Intel Architecture
IBF Input Buffer
ICH I/O Controller Hub
ICMB Intelligent Chassis Management Bus
IERR Internal Error
IFB I/O and Firmware Bridge
ILM Independent Loading Mechanism
IMC Integrated Memory Controller
INTR Interrupt
I/OAT I/O Acceleration Technology
IOH I/O Hub
IP Internet Protocol
IPMB Intelligent Platform Management Bus
IPMI Intelligent Platform Management Interface
IR Infrared
ITP In-Target Probe
KB 1024 bytes
KCS Keyboard Controller Style
KVM Keyboard, Video, Mouse
LAN Local Area Network
LCD Liquid Crystal Display
LDAP Local Directory Authentication Protocol
LED Light Emitting Diode
LPC Low Pin Count
LUN Logical Unit Number
MAC Media Access Control
MB 1024 KB
MCH Memory Controller Hub
Message Digest 2 – Hashing Algorithm
MD2
Message Digest 5 – Hashing Algorithm – Higher Security
MD5
ME Management Engine
MMU Memory Management Unit
ms Milliseconds
MTTR Memory Type Range Register
Mux Multiplexor
NIC Network Interface Controller
NMI Non-maskable Interrupt
OBF Output Buffer
OEM Original Equipment Manufacturer
Ohm Unit of electrical resistance
OVP Over-voltage Protection
138
Definition
Intel order number G13326-003
Intel® Server Board S1200BT TPS
Revision 1.0