Intel S1200BTS Specification page 37

Intel® Server Board S1200BT TPS

JTAG Master

Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are
SMBus 2.0 compliant.

Parallel general-purpose I/O Ports (16 direct, 32 shared)
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Serial general-purpose I/O Ports (80 in and 80 out)
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Three UARTs
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Platform Environmental Control Interface (PECI)
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Six general-purpose timers
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Interrupt controller
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Multiple SPI flash interfaces
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NAND/Memory interface
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Sixteen mailbox registers for communication between the Integrated BMC and host

LPC ROM interface
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Integrated BMC watchdog timer capability
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SD/MMC card controller with DMA support
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LED support with programmable blink rate controls on GPIOs

Port 80h snooping capability

Secondary Service Processor (SSP), which provides the HW capability of offloading
time critical processing tasks from the main ARM core.
Revision 1.0
Intel order number G13326-003
Functional Architecture
25