Correcting Link Failures; Switch Component Tests - HP A7533A - Brocade 4Gb SAN Switch Base Administrator's Manual

See Table 71 for a list of additional tests that can be used to determine the switch components that are not
functioning properly. See the Fabric OS Command Reference for additional command information.
Table 71

Switch component tests

Test
portloopbacktest
portregtest
spinsilk
sramretentiontest
portloopbacktest
turboramtest
statstest
Related Switch Test Option:
itemlist

Correcting link failures

A link failure occurs when a server or storage device is connected to a switch, but the link between the
server/storage and the switch does not come up. This prevents the server/storage from communicating
through the switch.
If the switchShow command or LEDs indicate that the link has not come up properly, use one or more of
the following procedures.
The port negotiates the link speed with the opposite side. The negotiation usually completes in one or two
seconds; however, sometimes the speed negotiation fails.
NOTE: Skip this procedure if the port speed is set to a static speed through the portCfgSpeed
command.
To determine if the negotiation was successfully completed:
1. Enter the portCfgShow command to display the port speed settings of all the ports.
2. Enter the switchShow command to determine if the port has module light.
3. Determine whether or not the port at 1 Gbps completes by entering the portCfgSpeed command.
Then change the port speed to 2 Gbps. This should correct the negotiation by setting to one speed.
4. Enter the portLogShow or portLogDump command.
5. Check the events area of the output:
14:38:51.976
14:39:39.227
• sn indicates a speed negotiation.
• NC indicates negotiation complete.
If these fields do not appear, proceed to the
Function
Performs a functional test of port N to N path.
Performs a read and write test of the ASIC SRAMs and registers.
Performs a functional test of internal and external transmit and receive paths
at full speed.
Verifies that the data written into the miscellaneous SRAMs in the ASIC are
retained after a 10-second wait.
Verifies the functional components of the switch.
Verifies that the on chip SRAM located in the 2 Gbps ASIC is using the
Turbo-Ram BIST circuitry. These same SRAMs are tested by portregtest
and sramretentiontest using PCI operations, but for this test the BIST
controller is able to perform the SRAM write and read operations at a much
faster rate.
Verifies the ASIC statistics counter logic.
Restricts the items to be tested to a smaller set of parameter values that you
pass to the switch.
SPEE sn <Port#> NC
SPEE sn
00000001,00000000,00000001
<Port#> NC 00000002,00000000,00000001
step 6.
Fabric OS 6.x administrator guide 317