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MICRO PANEL
VSD OPERATION AND CONTROLS (CON'T)
Pre-charge
When cooling is required (LCWT>SPHL), leaving
chilled liquid temp is greater than the setpoint high
limit), the chiller Control Board will send a Pre-Charge
Enable (2 enables on a 4 comp unit) via comms to the
VSD Logic Board. The VSD's DC bus voltage(s) across
the Bus Filter Capacitors will slowly be increased to
the proper level (>500VDC) through firing of the SCR
Trigger Board(s) and the associated pre-charge enable
control signal(s). The pre-charge time interval is fixed
at 20 seconds. The purpose of the precharge is to limit
current when charging an uncharged capacitor bank.
When uncharged, the capacitor bank looks like an
electrical short. The bus is brought up slowly by only
turning on the SCR's during the trailing half of the +
and – portion of the incoming AC sine wave. Follow-
ing is the status message displayed while the precharge
is taking place.
S YS X VSD DC BUS PRECHARGE
Following successful completion of the pre-charge
interval, the SCR's on the AC to DC semi-converter
(SCR/Diode Modules) will be gated fully on by the
SCR Trigger Board and the DC bus will be brought up
to its full potential. After pre-charge has been success-
fully completed, the SCR's will stay fully on until the
Chiller Control Board turns off the Pre-Charge Enable
via comms.
There will be a Unit Pre-charge Enable for 2 and 3 com-
pressor units and separate System Pre-charge Enables
for 4 compressor units.
The pre-charge will only take place when all of the fol-
lowing conditions are true, otherwise it is disabled:
· Daily Schedule is ON.
· Unit Switch is ON.
· System Switch(es) are ON.
· Run Permissive(s) are Enabled.
· Flow Switch indicates flow.
· LCHLT > Setpoint High Limit.
· Unit not faulted / locked out.
202
Run Mode / Unit Restart
In order to initiate a system run, two conditions must
be met. At least 1 of the 2 systems run signals from the
control panel must be present and at least 1 of the 4
possible Compressor RUN bits must be set in the serial
communications link between the VSD Logic Board
and the Chiller Control Board. Following successful
completion of pre-charge and receipt of the system run
signals, the motor output voltage (% modulation) and
output frequency commands will be determined by the
VSD microprocessor located on the VSD Logic Board.
These two parameters will be sent to the PWM generator
located on the VSD Logic Board for waveform process-
ing at a rate of once every 10 msec.
The voltage and frequency commands issued by the
VSD microprocessor are determined by the operating
frequency command received on the communications
link from the Chiller Control Board and by the present
operating frequency of the drive. Upon receipt of a legiti-
mate run command communication, the VSD's output
frequency will be increased from 0 Hz to the operating
frequency command from the communications link.
DC Bus Voltage Sensing and Scaling
Full DC Bus voltage and ½ DC Bus voltages are sensed
for up to 2 DC Buses. 2 and 3 compressor chillers share
a common DC Bus, while 4 compressor chillers utilize 2
DC Buses (1/3 and 2/4). The DC Bus is wired to the DC
Bus Isolation Board, the voltage is divided down through
a resistance voltage divider, and the reduced voltage is
fed to the VSD Logic Board for safety monitoring.
FORM 201.21-NM1 (1223)
JOHNSON CONTROLS
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