Pfi Filters - National Instruments PXI-6289 User Manual

Chapter 8 PFI

PFI Filters

You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal.
When the filters are enabled, your device samples the input on each rising edge of a filter clock.
M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency.
NI-DAQmx only supports filters on counter inputs.
Note
The following is an example of low to high transitions of the input signal. High to low transitions
work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes
from low to high, but glitches several times. When the filter clock has sampled the signal high
on N consecutive edges, the low to high transition is propagated to the rest of the circuit. The
value of N depends on the filter setting; refer to Table 8-1.
Filter Setting
125 ns
6.425 µs
2.56 ms
Disabled
The filter setting for each input can be configured independently. On power up, the filters are
disabled. Figure 8-3 shows an example of a low to high transition on an input that has its filter
set to 125 ns (N = 5).
RTSI, PFI, or
PXI_STAR Terminal
Filter Clock
(40 MHz)
Filtered Input
Enabling filters introduces jitter on the input signal. For the 125 ns and 6.425 µs filter settings,
the jitter is up to 25 ns. On the 2.56 ms setting, the jitter is up to 10.025 µs.
When a PFI input is routed directly to RTSI, or a RTSI input is routed directly to PFI, the
M Series device does not use the filtered version of the input signal.
8-4 | ni.com
Table 8-1. Filters
N (Filter Clocks
Needed to
Pass Signal)
5
257
~101,800
—
Figure 8-3. Filter Example
1 1 2 3 4
Pulse Width
Guaranteed to
Pass Filter
125 ns
6.425 µs
2.56 ms
—
1 2 3 4 5
Pulse Width
Guaranteed to
Not Pass Filter
100 ns
6.400 µs
2.54 ms
—
Filtered input goes
high when terminal
is sampled high on
five consecutive filter
clocks.