National Instruments PCI-6281 User Manual
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National Instruments PCI-6281 User Manual

Multifunction i/o modules and devices
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  • Page 1 PCI-6281...
  • Page 2 DAQ M Series M Series User Manual NI 622x, NI 625x, and NI 628x Multifunction I/O Modules and Devices M Series User Manual July 2016 371022L-01...
  • Page 3 11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 683 0100 NI Services For further support information, refer to the appendix. To comment on NI documentation, refer to the NI website at and enter the Info Code ni.com/info feedback © 2004–2016 National Instruments. All rights reserved.
  • Page 4 National Instruments Corporation. National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction.
  • Page 5 ™ The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is under license. The mark LabWindows is used under a license from Microsoft Corporation. Windows is a registered trademark of Microsoft Corporation in the United States and other countries.

  • Page 6: Table Of Contents

    68-Pin BNC Accessories .................. 2-6 68-Pin Screw Terminal Accessories..............2-6 RTSI Cables...................... 2-6 SCC Carriers and Accessories................2-6 SCXI ......................... 2-7 68-Pin Custom Cabling and Connectivity ............2-7 USB Device Accessories, USB Cable, and Power Supply....... 2-8 © National Instruments | v...
  • Page 7 Contents 37-Pin M Series Cables and Accessories..............2-8 37-Pin Cables....................2-9 37-Pin Screw Terminal Accessories ..............2-9 RTSI Cables ...................... 2-9 37-Pin Custom Cabling..................2-9 Signal Conditioning ......................2-10 Sensors and Transducers...................2-10 Signal Conditioning Options ..................2-10 SCXI ......................... 2-10 SCC........................
  • Page 8 AI Pause Trigger Signal ................... 4-31 Using a Digital Source..................4-32 Using an Analog Source ................... 4-32 Routing AI Pause Trigger Signal to an Output Terminal......... 4-32 Getting Started with AI Applications in Software............4-32 © National Instruments | vii...
  • Page 9 Contents Chapter 5 Analog Output AO Offset and AO Reference Selection ................5-2 Minimizing Glitches on the Output Signal ...............5-3 Analog Output Data Generation Methods ................ 5-3 Software-Timed Generations ..................5-3 Hardware-Timed Generations................... 5-4 Analog Output Triggering ....................5-5 Connecting Analog Output Signals .................. 5-5 Analog Output Timing Signals ..................
  • Page 10 Retriggerable Single Pulse Generation............. 7-20 Pulse Train Generation ..................... 7-21 Continuous Pulse Train Generation..............7-21 Finite Pulse Train Generation................7-22 Frequency Generation....................7-22 Using the Frequency Generator ................ 7-22 Frequency Division....................7-23 Pulse Generation for ETS ..................7-23 © National Instruments | ix...
  • Page 11 Contents Counter Timing Signals ....................7-24 Counter n Source Signal ...................7-24 Routing a Signal to Counter n Source .............. 7-25 Routing Counter n Source to an Output Terminal ..........7-25 Counter n Gate Signal....................7-25 Routing a Signal to Counter n Gate ..............7-26 Routing Counter n Gate to an Output Terminal ..........
  • Page 12 Triggering with an Analog Source ................... 11-2 APFI <0,1> Terminals....................11-2 Analog Input Channels ..................... 11-2 Analog Trigger Actions .................... 11-3 Routing Analog Comparison Event to an Output Terminal ........11-3 Analog Trigger Types....................... 11-3 Analog Trigger Accuracy ....................11-6 © National Instruments | xi...
  • Page 13 Contents Appendix A Module/Device-Specific Information NI 6220 ..........................A-2 NI 6221 (68-Pin) ....................... A-4 NI PCI-6221 (37-Pin) ....................... A-11 NI 6224 ..........................A-13 NI 6225 ..........................A-15 NI 6229 ..........................A-21 NI 6250 ..........................A-27 NI 6251 ..........................A-29 NI 6254 ..........................A-37 NI 6255 ..........................
  • Page 14 Figure A-29. USB-6281 Mass Termination Pinout ............ A-59 Figure A-30. PCI/PXI-6284 Pinout ................A-61 Figure A-31. PCI/PXI-6289 Pinout ................A-63 Figure A-32. USB-6289 Screw Terminal Pinout............A-65 Figure A-33. USB-6289 Mass Termination Pinout ............ A-67 © National Instruments | xiii...

  • Page 15: Getting Started

    Getting Started The M Series User Manual contains information about using the National Instruments M Series multifunction I/O data acquisition (DAQ) devices with NI-DAQmx 15.5 and later. M Series devices feature up to 80 analog input (AI) channels, up to four analog output (AO) channels, up to 48 lines of digital input/output (DIO), and two counters.

  • Page 16: Safety Guidelines For Hazardous Voltages

    Chapter 1 Getting Started Safety Guidelines for Hazardous Voltages If hazardous voltages are connected to the device/module, take the following precautions. A hazardous voltage is a voltage greater than 42.4 V or 60 VDC to earth ground. Caution Ensure that hazardous voltage wiring is performed only by qualified personnel adhering to local electrical standards.

  • Page 17: Hardware Symbol Definitions

    At the end of the product life cycle, all products must be sent to EU Customers a WEEE recycling center. For more information about WEEE recycling centers, National Instruments WEEE initiatives, and compliance with WEEE Directive 2002/96/EC on Waste and Electronic Equipment, visit ni.com/environment/...

  • Page 18: Device Self-Calibration

    Chapter 1 Getting Started To avoid ESD damage in handling the device, take the following precautions: • Ground yourself with a grounding strap or by touching a grounded object. • Touch the antistatic package to a metal part of your computer chassis before removing the device from the package.

  • Page 19: Getting Started With M Series Pci Express Devices And The Disk Drive Power Connector

    For example, consider using a disk drive power connector that is not in the same power chain as the hard drive. Figure 1-1. Connecting to the Disk Drive Power Connector Device Disk Drive Power Connector PC Disk Drive Power Connector © National Instruments | 1-5...

  • Page 20: Getting Started With M Series Usb Devices

    Chapter 1 Getting Started Replace the computer cover, and plug in and power on the computer. Self-calibrate the PCI Express DAQ device in MAX by following the instructions in the Device Self-Calibration section. Note Connecting or disconnecting the disk drive power connector can affect the analog performance of your device.
  • Page 21 USB-62xx BNC device, as shown in Figure 1-5. Use as short a wire as possible. In addition, the wires in the shielded cable that extend beyond the shield should be as short as possible. Figure 1-5. Grounding a USB-62 xx BNC Device through the CHS GND Screw Terminal © National Instruments | 1-7...

  • Page 22: Usb Device Panel/Wall Mounting

    Chapter 1 Getting Started USB Device Panel/Wall Mounting (USB-622 /625 /628 Devices) The Externally Powered USB M Series Panel Mounting Kit (part number 780214-01, not included in your USB-62xx kit) is an accessory you can use to mount the USB-62xx family of products to a panel or wall. USB Device LEDs LED Patterns Connector...

  • Page 23: Usb Device Fuse Replacement

    Remove the USB cable and all signal wires from the device. Loosen the four Phillips screws that attach the back lid to the enclosure and remove the lid. Replace the broken fuse while referring to Figure 1-8 for the fuse locations. © National Instruments | 1-9...
  • Page 24 Chapter 1 Getting Started Figure 1-8. USB-62 xx Screw Terminal Fuse Locations T 2A 250V (5 × 20 mm) Fuse Littelfuse 0453002 Fuse on USB-628 x Devices Replace the lid and screws. (USB-622 /625 BNC Devices) To replace a broken fuse in the USB-62xx BNC, complete the following steps.
  • Page 25 Remove the four Phillips 4-40 screws that attach the top panel to the enclosure and remove the panel and connector unit. Replace the broken fuse while referring to Figure 1-9 for the fuse location. Replace the top panel, screws, nut, and end pieces. © National Instruments | 1-11...

  • Page 26: Usb Device Security Cable Slot

    Chapter 1 Getting Started (USB-622 /625 /628 Mass Termination Devices) To replace a broken fuse in the USB-62xx Mass Termination, complete the following steps. Power down and unplug the device. Remove the USB cable and signal cable(s) from the device. Loosen the four Phillips screws that attach the lid to the enclosure and remove the lid.

  • Page 27: Installing A Ferrite

    Accessories and Cables NI offers a variety of accessories and cables to use with your multifunction I/O DAQ module Cables and Accessories DAQ System Overview, for device. Refer to the section of Chapter 2, more information. © National Instruments | 1-13...

  • Page 28: Daq System Overview

    I/O signals. Figure 2-2 features components common to all M Series devices. Figure 2-2. General M Series Block Diagram Analog Input Analog Output Digital Routing Digital I/O and Clock Interface Generation Counters RTSI © National Instruments | 2-1...

  • Page 29: Daq-Stc2 And Daq-6202

    Chapter 2 DAQ System Overview DAQ-STC2 and DAQ-6202 The DAQ-STC2 and DAQ-6202 implement a high-performance digital engine for M Series data acquisition hardware. Some key features of this engine include the following: • Flexible AI and AO sample and convert timing •...

  • Page 30: Cables And Accessories

    This section describes some cable and accessory options for M Series devices with one or two 68-pin connectors. Refer to the following sections for descriptions of these cables and accessories. Refer to for other accessory options. ni.com © National Instruments | 2-3...
  • Page 31 Chapter 2 DAQ System Overview Table 2-1. 68-Pin M Series Device/Module Cables and Accessories PCI, PCI Express, PXI, PXI Express USB Mass Termination Devices Devices and Modules 622x/625x/ 628x 622x/625x/ Connector 0 628x Connector 0 6224/6229/ 6254/6259/ 6229/6259/ Cables and Accessories 6284/6289 6225/6255 6289...

  • Page 32: 68-Pin Cables

    NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable works with PCI/PCI Express/PXI/PXI Express devices and modules. NI recommends that you use the SH68-68-EPM cable; however, an SH68-68-EP cable will work with USB Mass Termination devices. © National Instruments | 2-5...

  • Page 33: 68-Pin Bnc Accessories

    Chapter 2 DAQ System Overview 68-Pin BNC Accessories You can use your 68-pin cable to connect your DAQ device to the following BNC accessories: BNC-2110—Provides BNC connectivity to all analog signals, some digital signals, and • spring terminals for other digital signals BNC-2111—Provides BNC connectivity to 16 single-ended analog input signals, •...

  • Page 34: Scxi

    When using a cable shield, use separate shields for the analog and digital sections of the cable. To prevent noise when using a cable shield, use separate shields for the analog and digital sections of the cable. © National Instruments | 2-7...

  • Page 35: Usb Device Accessories, Usb Cable, And Power Supply

    Chapter 2 DAQ System Overview For more information on the connectors used for DAQ devices, refer to the NI DAQ Device Custom Cables, Replacement Connectors, and Screws document by going to ni.com/info and entering the Info Code rdspmb USB Device Accessories, USB Cable, and Power Supply USB Screw Terminal and USB Mass Termination devices feature connectivity directly on the device and do not require an accessory for interfacing to signals.

  • Page 36: 37-Pin Cables

    R37F-37M—37-pin female-to-male ribbon I/O cable • 37-Pin Screw Terminal Accessories National Instruments offers several styles of screw terminal connector blocks. Use your 37-pin cable to connect a PCI-6221 (37-pin) device to one of the following connector blocks: CB-37F-HVD—37-pin DIN rail screw terminal block •...

  • Page 37: Signal Conditioning

    Chapter 2 DAQ System Overview Signal Conditioning Many sensors and transducers require signal conditioning before a measurement system can effectively and accurately acquire the signal. The front-end signal conditioning system can include functions such as signal amplification, attenuation, filtering, electrical isolation, simultaneous sampling, and multiplexing.

  • Page 38: Scc

    Terminal, or USB-622x/625x BNC devices. Programming Devices in Software National Instruments measurement devices are packaged with NI-DAQmx driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows™/CVI™, to program all the features of your NI measurement devices.
  • Page 39 Chapter 2 DAQ System Overview M Series devices use the NI-DAQmx driver. NI-DAQmx includes a collection of programming examples to help you get started developing an application. You can modify example code and save it in an application. You can use examples to develop a new application or add example code to an existing application.

  • Page 40: Connector And Led Information

    M Series USB device LEDs. Module/Device-Specific Information, for device I/O Note Refer to Appendix A, connector pinouts. I/O Connector Signal Descriptions Table 3-1 describes the signals found on the I/O connectors. Not all signals are available on all devices. © National Instruments | 3-1...
  • Page 41 Chapter 3 Connector and LED Information Table 3-1. I/O Connector Signals Signal Name Reference Direction Description Analog Input Ground—These terminals are the AI GND — — reference point for single-ended AI measurements in RSE mode and the bias current return point for DIFF measurements.
  • Page 42 As a Port 1 digital I/O signal, you can individually configure each signal as an input or output. Connecting Digital I/O Signals Refer to the Digital I/O, or to Chapter 8, section of Chapter 6, PFI. © National Instruments | 3-3...
  • Page 43 Chapter 3 Connector and LED Information Table 3-1. I/O Connector Signals (Continued) Signal Name Reference Direction Description Programmable Function Interface or Port 2 PFI <8..15>/ D GND Input or Digital I/O Channels—Each of these terminals P2.<0..7> Output can be individually configured as a PFI terminal or a digital I/O terminal.

  • Page 44: +5 V Power Source

    I/O signal of your choice. The USER 1 and USER 2 BNC connectors are routed (internal to the USB BNC device) to the USER 1 and USER 2 screw terminals, as shown in Figure 3-1. © National Instruments | 3-5...
  • Page 45 Chapter 3 Connector and LED Information Figure 3-1. USER 1 and USER 2 BNC Connections USER 1 BNC USER 2 BNC D GND D GND USER 1 Internal Connection USER 2 D GND +5 V D GND P0.0 P0.1 Screw P0.2 Terminal P0.3...

  • Page 46: Rtsi Connector Pinout

    The device is configured, but there is no activity over the bus. The device is configured and there is activity over the bus. Blinking USB-625x/628x BNC devices only. © National Instruments | 3-7...

  • Page 47: Analog Input

    M Series devices can sample channels in any order at the maximum conversion rate, and you can individually program each channel in a sample with a different input range. © National Instruments | 4-1...

  • Page 48: Analog Input Range

    Chapter 4 Analog Input A/D Converter—The analog-to-digital converter (ADC) digitizes the AI signal by • converting the analog voltage into a digital number. AI FIFO—M Series devices can perform both single and multiple A/D conversions of a • fixed or infinite number of samples. A large first-in-first-out (FIFO) buffer holds data during AI acquisitions to ensure that no data is lost.

  • Page 49: Analog Input Lowpass Filter

    Nyquist frequency. For example, if the signal of interest does not have frequency components beyond 40 kHz, then using a filter with a cutoff frequency at 40 kHz attenuates noise beyond the cutoff that is not of interest. The cutoff © National Instruments | 4-3...

  • Page 50: Analog Input Ground-Reference Settings

    Chapter 4 Analog Input frequency of the lowpass filter is also called the small signal bandwidth. The specifications document for your DAQ device lists the small signal bandwidth. On some devices, the filter cutoff is fixed. On other devices, this filter is programmable and can be enabled for a lower frequency.
  • Page 51 Exceeding the maximum input voltage of AI signals distorts the measurement results. Exceeding the maximum input voltage rating also can damage the device and the computer. NI is not liable for any damage resulting from such signal connections. © National Instruments | 4-5...

  • Page 52: Configuring Ai Ground-Reference Settings In Software

    Chapter 4 Analog Input AI ground-reference setting is sometimes referred to as AI terminal configuration. Configuring AI Ground-Reference Settings in Software You can program channels on an M Series device to acquire with different ground references. To enable multimode scanning in LabVIEW, use the NI-DAQmx Create Virtual Channel VI of the NI-DAQmx API.
  • Page 53 The capacitance of the cable also can increase the settling time. National Instruments recommends using individually shielded, twisted-pair wires that are Connecting Analog Input 2 m or less to connect AI signals to the device. Refer to the Signals section for more information.
  • Page 54 Chapter 4 Analog Input Consider again the example above where a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1. Suppose the input range for channel 0 is -10 V to 10 V and the input range of channel 1 is -200 mV to 200 mV. You can connect channel 2 to AI GND (or you can use the internal ground;...

  • Page 55: Analog Input Data Acquisition Methods

    Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. Continuous acquisition is also referred to as double-buffered or circular-buffered acquisition. © National Instruments | 4-9...

  • Page 56: Analog Input Triggering

    Chapter 4 Analog Input If data cannot be transferred across the bus fast enough, the FIFO becomes full. New acquisitions overwrite data in the FIFO before it can be transferred to host memory. The device generates an error in this case. With continuous operations, if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer, the buffer could reach an overflow condition, causing an error to be generated.

  • Page 57: Connecting Analog Input Signals

    Analog Input Ground-Reference Settings Refer to the section for descriptions of the RSE, NRSE, and DIFF modes and software considerations. Connecting Ground-Referenced Signal Sources † Refer to the section for more information. © National Instruments | 4-11...

  • Page 58: Connecting Floating Signal Sources

    Chapter 4 Analog Input Connecting Floating Signal Sources What Are Floating Signal Sources? A floating signal source is not connected to the building ground system, but has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers.

  • Page 59: When To Use Referenced Single-Ended (Rse) Connections With Floating Signal Sources

    This connection works well for DC-coupled sources with low source impedance (less than 100 Ω). Note (NI USB-62xx BNC Devices) To measure a floating signal source on USB BNC devices, move the switch under the BNC connector to the FS position. © National Instruments | 4-13...
  • Page 60 Chapter 4 Analog Input Figure 4-4. Differential Connections for Floating Signal Sources without Bias Resistors M Series Device Floating Signal Source – AI– Impedance AI SENSE <100 Ω AI GND However, for larger source impedances, this connection leaves the DIFF signal path significantly off balance.
  • Page 61 Figure 4-7. © National Instruments | 4-15...

  • Page 62: Using Non-Referenced Single-Ended (Nrse) Connections For Floating Signal Sources

    Chapter 4 Analog Input Figure 4-7. Differential Connections for AC Coupled Floating Sources with Balanced Bias Resistors M Series Device AC Coupling AC Coupled Floating Signal Source – AI– AI SENSE AI GND Using Non-Referenced Single-Ended (NRSE) Connections for Floating Signal Sources It is important to connect the negative lead of a floating signals source to AI GND (either directly or through a resistor).

  • Page 63: Using Referenced Single-Ended (Rse) Connections For Floating Signal Sources

    If a grounded signal source is incorrectly measured, this difference can appear as measurement error. Follow the connection instructions for grounded signal sources to eliminate this ground potential difference from the measured signal. © National Instruments | 4-17...

  • Page 64: When To Use Differential Connections With Ground-Referenced Signal Sources

    Chapter 4 Analog Input When to Use Differential Connections with Ground-Referenced Signal Sources Use DIFF input connections for any channel that meets any of the following conditions: • The input signal is low level (less than 1 V). • The leads connecting the signal to the device are greater than 3 m (10 ft). •...

  • Page 65: When To Use Referenced Single-Ended (Rse) Connections With Ground-Referenced Signal Sources

    With this type of connection, the NI-PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as V in the figure. AI+ and AI- must both remain within ±11 V of AI GND. © National Instruments | 4-19...

  • Page 66: Using Non-Referenced Single-Ended (Nrse) Connections For Ground-Referenced Signal Sources

    Chapter 4 Analog Input Using Non-Referenced Single-Ended (NRSE) Connections for Ground-Referenced Signal Sources Figure 4-11 shows how to connect ground-reference signal sources in NRSE mode. Figure 4-11. Single-Ended Connections for Ground-Referenced Signal Sources (NRSE Configuration) I/O Connector AI <0..15> or AI <16.. n > Ground- Referenced Instrumentation...

  • Page 67: Field Wiring Considerations

    AI Sample Clock Event Timebase Programmable 20 MHz Timebase Clock Divider 100 kHz Timebase PFI, RTSI PXI_CLK10 PXI_STAR Analog Comparison Event AI Convert Clock Ctr n Internal Output AI Convert Clock Programmable Timebase Clock Divider © National Instruments | 4-21...
  • Page 68 Chapter 4 Analog Input M Series devices use AI Sample Clock (ai/SampleClock) and AI Convert Clock (ai/ConvertClock) to perform interval sampling. As Figure 4-13 shows, AI Sample Clock (ai/SampleClock) controls the sample period, which is determined by the following equation: 1/Sample Period = Sample Rate Figure 4-13.

  • Page 69: Ai Sample Clock Signal

    Clock. A measurement acquisition consists of one or more samples. You can specify an internal or external source for AI Sample Clock. You also can specify whether the measurement sample begins on the rising edge or falling edge of AI Sample Clock. © National Instruments | 4-23...

  • Page 70: Using An Internal Source

    Chapter 4 Analog Input Using an Internal Source One of the following internal signals can drive AI Sample Clock: Counter n Internal Output • • AI Sample Clock Timebase (divided down) • A pulse initiated by host software A programmable internal counter divides down the sample clock timebase. Several other internal signals can be routed to AI Sample Clock through RTSI.

  • Page 71: Ai Sample Clock Timebase Signal

    You can specify either an internal or external signal as the source of AI Convert Clock. You also can specify whether the measurement sample begins on the rising edge or falling edge of AI Convert Clock. © National Instruments | 4-25...

  • Page 72: Using An Internal Source

    Chapter 4 Analog Input NI-DAQmx chooses the fastest conversion rate possible based on the speed of the A/D converter and adds 10 μs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time.

  • Page 73: Using A Delay From Sample Clock To Convert Clock

    Figure 4-18. AI Sample Clock Pulses Are Gated Off; AI Sample Clock Too Fast For Convert Clock AI Sample Clock AI Convert Clock Channel Measured 1 2 3 1 2 3 1 2 3 Sample #1 Sample #2 Sample #3 © National Instruments | 4-27...
  • Page 74 Chapter 4 Analog Input Figure 4-19. AI Convert Clock Too Fast For AI Sample Clock; AI Convert Clock Pulses Are Gated Off AI Sample Clock AI Convert Clock 1 2 3 1 2 3 1 2 3 Channel Measured Sample #1 Sample #2 Sample #3 Figure 4-20.

  • Page 75: Ai Convert Clock Timebase Signal

    To use AI Start Trigger with a digital source, specify a source and an edge. The source can be any of the following signals: • PFI <0..15> • RTSI <0..7> Counter n Internal Output • • PXI_STAR © National Instruments | 4-29...

  • Page 76: Using An Analog Source

    Chapter 4 Analog Input The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more information. You also can specify whether the measurement acquisition begins on the rising edge or falling edge of AI Start Trigger.

  • Page 77: Using A Digital Source

    The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive. You can program the active level of the pause trigger to be high or low. © National Instruments | 4-31...

  • Page 78: Using A Digital Source

    Chapter 4 Analog Input Using a Digital Source To use AI Pause Trigger, specify a source and a polarity. The source can be any of the following signals: • PFI <0..15> • RTSI <0..7> • PXI_STAR The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more information.

  • Page 79: Analog Output

    AO Sample Clock—The AO Sample Clock signal reads a sample from the DAC FIFO and • generates the AO voltage. AO Offset and AO Reference Selection—AO offset and AO reference selection signals • allow you to change the range of the analog outputs. © National Instruments | 5-1...

  • Page 80: Ao Offset And Ao Reference Selection

    Chapter 5 Analog Output AO Offset and AO Reference Selection AO offset and AO reference selection allow you to set the AO range. The AO range describes the set of voltages the device can generate. The digital codes of the DAC are spread evenly across the AO range.

  • Page 81: Minimizing Glitches On The Output Signal

    Software-timed generations are also referred to as immediate or static operations. They are typically used for writing a single value out, such as a constant DC voltage. © National Instruments | 5-3...

  • Page 82: Hardware-Timed Generations

    Chapter 5 Analog Output Hardware-Timed Generations With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally. Hardware-timed generations have several advantages over software-timed acquisitions: •...

  • Page 83: Analog Output Triggering

    AO GND AO GND Load V OUT Load V OUT AO 1 AO 3 Channel 1 Channel 3 Connector 0 (AI 0 –15) M Series Device Connector 1 (AI 16 – 31) M Series Device © National Instruments | 5-5...

  • Page 84: Analog Output Timing Signals

    Chapter 5 Analog Output Analog Output Timing Signals Figure 5-3 summarizes all of the timing options provided by the analog output timing engine. Figure 5-3. Analog Output Timing Options PFI, RTSI PFI, RTSI PXI_STAR AO Sample Clock PXI_STAR Analog Comparison Event Analog Comparison Ctr n Internal Output Event...

  • Page 85: Using An Analog Source

    Figure 5-5. Figure 5-5. AO PauseTrigger with Other Signal Source Pause Trigger Sample Clock © National Instruments | 5-7...

  • Page 86: Using A Digital Source

    Chapter 5 Analog Output Using a Digital Source To use AO Pause Trigger, specify a source and a polarity. The source can be one of the following signals: • PFI <0..15> • RTSI <0..7> • PXI_STAR The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more information.

  • Page 87: Routing Ao Sample Clock Signal To An Output Terminal

    • 100 kHz Timebase • PXI_CLK10 • PFI <0..15> • RTSI <0..7> • PXI_STAR • Analog Comparison Event (an analog trigger) AO Sample Clock Timebase is not available as an output on the I/O connector. © National Instruments | 5-9...

  • Page 88: Getting Started With Ao Applications In Software

    Chapter 5 Analog Output You might use AO Sample Clock Timebase if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal, but do not need to divide the signal, then you should use AO Sample Clock rather than AO Sample Clock Timebase.

  • Page 89: Digital I/O

    P0. x I/O Protection DO. x Direction Control Weak Pull-Down Static DI DI Waveform Measurement FIFO DI Sample Clock DI Change Detection The DIO terminals are named P0.<0..31> on the M Series device I/O connector. © National Instruments | 6-1...

  • Page 90: Static Dio

    Chapter 6 Digital I/O The voltage input and output levels and the current drive levels of the DIO lines are listed in the specifications of your device. Static DIO Each of the M Series DIO lines can be used as a static DI or DO line. You can use static DIO lines to monitor or control digital signals.

  • Page 91: Digital Waveform Acquisition

    • DI Change Detection Output Several other internal signals can be routed to DI Sample Clock through RTSI. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help for more information. © National Instruments | 6-3...

  • Page 92: Using An External Source

    Chapter 6 Digital I/O Using an External Source You can route any of the following signals as DI Sample Clock: • PFI <0..15> • RTSI <0..7> • PXI_STAR • Analog Comparison Event (an analog trigger) You can sample data on the rising or falling edge of DI Sample Clock. Routing DI Sample Clock to an Output Terminal You can route DI Sample Clock out to any PFI terminal.

  • Page 93: Using An Internal Source

    If you configure a PFI or DIO line as an output, understand the current requirements of the load connected to these signals. Do not exceed the specified current output limits of the DAQ device. NI has several signal conditioning solutions for digital applications requiring high current drive. © National Instruments | 6-5...

  • Page 94: Programmable Power-Up States

    Chapter 6 Digital I/O • If you configure a PFI or DIO line as an input, do not drive the line with voltages outside of its normal operating range. The PFI or DIO lines have a smaller operating range than the AI signals.

  • Page 95: Di Change Detection

    Drive any RTSI <0..7>, PFI <0..15>, or PXI_STAR signal • Drive the DO Sample Clock or DI Sample Clock • Generate an interrupt The Change Detection Event signal also can be used to detect changes on digital output events. © National Instruments | 6-7...

  • Page 96: Di Change Detection Applications

    Chapter 6 Digital I/O DI Change Detection Applications The DIO change detection circuitry can interrupt a user program when one of several DIO signals changes state. You also can use the output of the DIO change detection circuitry to trigger a DI or counter acquisition on the logical OR of several digital signals.

  • Page 97: Getting Started With Dio Applications In Software

    Static digital output • Digital waveform generation • Digital waveform acquisition • DI change detection Note For more information about programming digital I/O applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW Help. © National Instruments | 6-9...

  • Page 98: Counter Input Applications

    For information about connecting counter signals, refer to the section. Counter Input Applications The following sections list the various counter input applications available on M Series devices: Counting Edges • Pulse-Width Measurement • Period Measurement • Semi-Period Measurement • © National Instruments | 7-1...

  • Page 99: Counting Edges

    Chapter 7 Counters Frequency Measurement • Position Measurement • Two-Signal Edge-Separation Measurement • Counting Edges In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can Controlling the Direction of control the direction of counting (up or down) as described in the Counting...

  • Page 100: Buffered (Sample Clock) Edge Counting

    You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active. © National Instruments | 7-3...

  • Page 101: Single Pulse-Width Measurement

    Chapter 7 Counters You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter. A pulse-width measurement will be accurate even if the counter is armed while a pulse train is in progress.

  • Page 102: Period Measurement

    Source input occurring between two active edges of the Gate input. On the second active edge of the Gate input, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then reads the stored count. © National Instruments | 7-5...

  • Page 103: Buffered Period Measurement

    Chapter 7 Counters Figure 7-7 shows an example of a single period measurement. Figure 7-7. Single Period Measurement GATE SOURCE Counter Value HW Save Register Buffered Period Measurement Buffered period measurement is similar to single period measurement, but buffered period measurement measures multiple periods.

  • Page 104: Semi-Period Measurement

    Gate input. In most applications, this first point should be discarded. Figure 7-9 shows an example of a buffered semi-period measurement. Figure 7-9. Buffered Semi-Period Measurement Counter Armed GATE SOURCE Counter Value Buffer © National Instruments | 7-7...

  • Page 105: Frequency Measurement

    Chapter 7 Counters Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention, Duplicate Count Prevention described in the section.

  • Page 106: Low Frequency With One Counter (Averaged)

    Route the signal to measure (F1) to the Source of the counter. Configure the counter for a single pulse-width measurement. If you measure the width of pulse T to be N periods of F1, the frequency of F1 is N/T. © National Instruments | 7-9...

  • Page 107: Large Range Of Frequencies With Two Counters

    Chapter 7 Counters Figure 7-12 illustrates this method. Another option is to measure the width of a known period instead of a known pulse. Figure 7-12. High Frequency with Two Counters Width of Pulse (T) Pulse Pulse Gate … Source Pulse-Width Width of Measurement...

  • Page 108: Choosing A Method For Measuring Frequency

    (fk), but the divide down means that the measurement time is the period of the divided down signal, or N/fx where N is the divide down. © National Instruments | 7-11...
  • Page 109 Chapter 7 Counters Table 7-1. Frequency Measurement Methods One Counter Two Counters High Variable — Averaged Frequency Large Range Known Known timebase Known timebase ------------------------------- timebase gating period --- - ------------ - --- - gating period Maximum × -------------- - ×...
  • Page 110 The advantage of this method is that it requires only one counter. Disadvantages include the possibility of FIFO overflow at high frequencies and high N for this method. These measurements take more time and consume some of the available PCI or PXI © National Instruments | 7-13...

  • Page 111: Position Measurement

    Chapter 7 Counters bandwidth; if such bandwidth is not available due to other measurements taking place, this method may fail to transfer all the required samples to perform the measurement. • Using two counters for high frequency measurements is accurate for high frequency signals.

  • Page 112: Measurements Using Quadrature Encoders

    A and B for X4 encoding. Whether the counter increments or decrements depends on which channel leads the other. Each cycle results in four increments or decrements, as shown in Figure 7-16. Figure 7-16. X4 Encoding Ch A Ch B Counter Value © National Instruments | 7-15...

  • Page 113: Measurements Using Two Pulse Encoders

    Chapter 7 Counters Channel Z Behavior Some quadrature encoders have a third channel, channel Z, which is also referred to as the index channel. A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle.

  • Page 114: Buffered (Sample Clock) Position Measurement

    Use this type of measurement to count events or measure the time that occurs between edges on two signals. This type of measurement is sometimes referred to as start/stop trigger measurement, second gate measurement, or A-to-B measurement. © National Instruments | 7-17...

  • Page 115: Single Two-Signal Edge-Separation Measurement

    Chapter 7 Counters Refer to the following sections for more information about the M Series edge-separation measurement options: Single Two-Signal Edge-Separation Measurement • Buffered Two-Signal Edge-Separation Measurement • Single Two-Signal Edge-Separation Measurement With single two-signal edge-separation measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal.

  • Page 116: Counter Output Applications

    Figure 7-22 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source). Figure 7-22. Single Pulse Generation Counter Armed SOURCE © National Instruments | 7-19...

  • Page 117: Single Pulse Generation With Start Trigger

    Chapter 7 Counters Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal. The pulse appears on the Counter n Internal Output signal of the counter. You can route the Start Trigger signal to the Gate input of the counter.

  • Page 118: Pulse Train Generation

    M and N periods, then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M + N. Default Counter/Timer Pinouts For information about connecting counter signals, refer to the section. © National Instruments | 7-21...

  • Page 119: Finite Pulse Train Generation

    Chapter 7 Counters Finite Pulse Train Generation This function generates a train of pulses of predetermined duration. This counter operation requires both counters. The first counter (for this example, Counter 0) generates a pulse of desired width. The second counter, Counter 1, generates the pulse train, which is gated by the pulse of the first counter.

  • Page 120: Frequency Division

    120; the process will repeat in this manner until the counter is disarmed. The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress. © National Instruments | 7-23...

  • Page 121: Counter Timing Signals

    Chapter 7 Counters The waveform thus produced at the counter’s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the Nyquist frequency of the system. Figure 7-29 shows an example of pulse generation for ETS;...

  • Page 122: Routing A Signal To Counter N Source

    You can route Counter n Source out to any PFI <0..15> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup. Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents. © National Instruments | 7-25...

  • Page 123: Routing A Signal To Counter N Gate

    Chapter 7 Counters Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal. Any of the following signals can be routed to the Counter n Gate input: • RTSI <0..7> • PFI <0..15>...

  • Page 124: Counter N A, Counter N B, And Counter N Z Signals

    Counter n HW Arm input of the counter. Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input: • RTSI <0..7> • PFI <0..15> © National Instruments | 7-27...

  • Page 125: Counter N Internal Output And Counter N Tc Signals

    Chapter 7 Counters • AI Reference Trigger (ai/ReferenceTrigger) • AI Start Trigger (ai/StartTrigger) • PXI_STAR • Analog Comparison Event Counter 1 Internal Output can be routed to Counter 0 HW Arm. Counter 0 Internal Output can be routed to Counter 1 HW Arm. Some of these options may not be available in some driver software.

  • Page 126: Counter Triggering

    Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter. ArmStart.DigEdge.Edge is not supported on M Series devices and modules. © National Instruments | 7-29...

  • Page 127: Other Counter Features

    Chapter 7 Counters For counter output operations, you can use it in addition to the start and pause triggers. For counter input operations, you can use the arm start trigger to have start trigger-like behavior. The arm start trigger can be used for synchronizing multiple counter input and output tasks.
  • Page 128 M Series device does not use the filtered version of the input signal. Refer to the KnowledgeBase document, Digital Filtering with M Series and CompactDAQ, for more information about digital filters and counters. To access this KnowledgeBase, go to and enter the Info Code ni.com/info rddfms © National Instruments | 7-31...

  • Page 129: Prescaling

    Chapter 7 Counters Prescaling Prescaling allows the counter to count a signal that is faster than the maximum timebase of the counter. M Series devices offer 8X and 2X prescaling on each counter (prescaling can be disabled). Each prescaler consists of a small, simple counter that counts to eight (or two) and rolls over.

  • Page 130: Example Application That Works Correctly (No Duplicate Counting)

    In Figure 7-33, after the first rising edge of Gate, no Source pulses occur, so the counter does not write the correct data to the buffer. Figure 7-33. Duplicate Count Example No Source edge, so no value written to buffer. Gate Source Counter Value Buffer © National Instruments | 7-33...

  • Page 131: Example Application That Prevents Duplicate Count

    Chapter 7 Counters Example Application That Prevents Duplicate Count With duplicate count prevention enabled, the counter synchronizes both the Source and Gate signals to the 80 MHz Timebase. By synchronizing to the timebase, the counter detects edges on the Gate even if the Source does not pulse. This enables the correct current count to be stored in the buffer even if no Source edges occur between Gate signals, as shown in Figure 7-34.

  • Page 132: Enabling Duplicate Count Prevention In Ni-Daqmx

    80 MHz Timebase 80 MHz Source All Except Position 20 MHz Timebase, Other Internal Measurement 100 kHz Timebase, Source or PXI_CLK10 All Except Position Any Other Signal External Source Measurement (such as PFI or RTSI) © National Instruments | 7-35...

  • Page 133: 80 Mhz Source Mode

    Chapter 7 Counters 80 MHz Source Mode In 80 MHz source mode, the device synchronizes signals on the rising edge of the source, and counts on the following rising edge of the source, as shown in Figure 7-35. Figure 7-35. 80 MHz Source Mode Source Synchronize Count...

  • Page 134: Pfi

    0 to 15). When a terminal is used as a static digital input or output, it is called P1.x or P2.x. On the I/O connector, each terminal is labeled PFI x/P1 or PFI x/P2. © National Instruments | 8-1...

  • Page 135: Using Pfi Terminals As Timing Input Signals

    Chapter 8 The voltage input and output levels and the current drive levels of the PFI signals are listed in the specifications of your device. Using PFI Terminals as Timing Input Signals Use PFI terminals to route external timing signals to many different M Series functions. Each PFI terminal can be routed to any of the following signals: •...

  • Page 136: Using Pfi Terminals As Static Digital I/Os

    PFI 0 source and an external PFI 2 source to two PFI terminals. Figure 8-2. PFI Input Signals Connections PFI 0 PFI 2 PFI 0 PFI 2 Source Source D GND I/O Connector M Series Device © National Instruments | 8-3...

  • Page 137: Pfi Filters

    Chapter 8 PFI Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency. NI-DAQmx only supports filters on counter inputs.

  • Page 138: I/O Protection

    When using your M Series device to control an SCXI chassis, DIO lines 0, 1, 2, and 4 are used as communication lines and must be left to power-up in the default high-impedance state to avoid potential damage to these signals. © National Instruments | 8-5...

  • Page 139: Clock Routing

    Figure 9-1. M Series Clock Routing Circuitry Onboard 10 MHz RefClk (To RTSI <0..7> 80 MHz ÷ 10 Output Selectors) Oscillator External 80 MHz Reference Timebase RTSI <0..7> Clock 20 MHz ÷ PXIe_CLK10 Timebase PXI_STAR 100 kHz ÷ Timebase © National Instruments | 9-1...

  • Page 140: 80 Mhz Timebase

    Chapter 9 Digital Routing and Clock Generation 80 MHz Timebase The 80 MHz Timebase can be used as the Source input to the 32-bit general-purpose counter/timers. The 80 MHz Timebase is generated from the following sources: • Onboard oscillator • External signal (by using the external reference clock) 20 MHz Timebase The 20 MHz Timebase normally generates many of the AI and AO timing signals.

  • Page 141: Synchronizing Multiple Devices

    Once all of the devices are using or referencing a common timebase, you can synchronize operations across them by sending a common start trigger out across the PFI bus and setting their sample clock rates to the same value. © National Instruments | 9-3...

  • Page 142: Real-Time System Integration (Rtsi)

    Use a common clock (or timebase) to drive the timing engine on multiple devices • Share trigger signals between devices Many National Instruments DAQ, Motion, Vision, and CAN devices support RTSI. RTSI is not supported on USB devices. Note In a PCI/PCI Express system, the RTSI bus consists of the RTSI bus interface and a ribbon cable.

  • Page 143: Using Rtsi As Outputs

    Counter n Source, Gate, Z, Internal Output • • Change Detection Event • Analog Comparison Event • FREQ OUT • PFI <0..5> Note Signals with a * are inverted before being driven on the RTSI terminals. © National Instruments | 9-5...

  • Page 144: Using Rtsi Terminals As Timing Input Signals

    Chapter 9 Digital Routing and Clock Generation Using RTSI Terminals as Timing Input Signals You can use RTSI terminals to route external timing signals to many different M Series functions. Each RTSI terminal can be routed to any of the following signals: •...
  • Page 145 M Series device does not use the filtered version of the input signal. Refer to the KnowledgeBase document, Digital Filtering with M Series and CompactDAQ, for more information about digital filters and counters. To access this KnowledgeBase, go to and enter the Info Code ni.com/info rddfms © National Instruments | 9-7...

  • Page 146: Pxi Clock And Trigger Signals

    Chapter 9 Digital Routing and Clock Generation PXI Clock and Trigger Signals PXI clock and trigger signals are only available on PXI/PXI Express devices. PXI_CLK10 PXI_CLK10 is a common low-skew 10 MHz reference clock for synchronization of multiple modules in a PXI measurement or control system. The PXI backplane is responsible for generating PXI_CLK10 independently to each peripheral slot in a PXI chassis.
  • Page 147 M Series device does not use the filtered version of the input signal. Refer to the KnowledgeBase document, Digital Filtering with M Series and CompactDAQ, for more information about digital filters and counters. To access this KnowledgeBase, go to and enter the Info Code ni.com/info rddfms © National Instruments | 9-9...

  • Page 148: Bus Interface

    NI M Series PCI/PCIe/PXI/PXIe devices have six fully-independent DMA controllers for high-performance transfers of data blocks. One DMA controller is available for each measurement and acquisition block: – Analog input – Analog output – Counter 0 © National Instruments | 10-1...

  • Page 149: Usb Device Data Transfer Methods

    Chapter 10 Bus Interface – Counter 1 – Digital waveform generation (digital output) – Digital waveform acquisition (digital input) Each DMA controller channel contains a FIFO and independent processes for filling and emptying the FIFO. This allows the buses involved in the transfer to operate independently for maximum performance.

  • Page 150: Pxi Considerations

    Slot-Compatible PXI-1 Peripheral Modules. Refer to your device specifications to see if your PXI M Series device is hybrid slot-compatible. 3U designates devices that are 100 mm tall (as opposed to the taller 6U modules). © National Instruments | 10-3...

  • Page 151: Using Pxi With Compactpci

    Chapter 10 Bus Interface Hybrid slot-compatible defines where the device can be installed. PXI M Series devices can be installed in the following chassis and slots: PXI chassis—PXI M Series devices can be installed in any peripheral slot of a PXI chassis. •...

  • Page 152: Triggering

    You also can program your DAQ device to perform an action in response to a trigger from a digital source. The action can affect the following: • Analog input acquisition • Analog output generation • Counter behavior • Digital waveform acquisition and generation © National Instruments | 11-1...

  • Page 153: Triggering With An Analog Source

    Chapter 11 Triggering Triggering with an Analog Source Some M Series devices can generate a trigger on an analog signal. To find your device triggering options, refer to the specifications document for your device. Figure 11-2 shows the analog trigger circuit. Figure 11-2.

  • Page 154: Analog Trigger Actions

    In below-level analog triggering mode, shown in Figure 11-3, the trigger is generated when the signal value is less than Level. Figure 11-3. Below-Level Analog Triggering Mode Level Analog Comparison Event © National Instruments | 11-3...
  • Page 155 Chapter 11 Triggering In above-level analog triggering mode, shown in Figure 11-4, the trigger is generated when the signal value is greater than Level. Figure 11-4. Above-Level Analog Triggering Mode Level Analog Comparison Event Analog Edge Triggering with Hysteresis—Hysteresis adds a programmable voltage •...
  • Page 156 Specify the levels by setting the window Top value and the window Bottom value. Figure 11-7 demonstrates a trigger that asserts when the signal enters the window. Figure 11-7. Analog Window Triggering Mode (Entering Window) Bottom Analog Comparison Event © National Instruments | 11-5...

  • Page 157: Analog Trigger Accuracy

    Chapter 11 Triggering Analog Trigger Accuracy The analog trigger circuitry compares the voltage of the trigger source to the output of programmable trigger DACs. When you configure the level (or the high and low limits in window trigger mode), the device adjusts the output of the trigger DACs. Refer to the specifications document for your device to find the accuracy or resolution of these DACs, which also shows the accuracy or resolution of analog triggers.
  • Page 158 Note M Series devices may be used with most E Series accessories. However, some E Series accessories use different terminal names. Refer to Appendix D, Upgrading from E Series to M Series, for more information. © National Instruments | A-1...

  • Page 159: Figure A-1. Pci/Pxi-6220 Pinout

    Appendix A Module/Device-Specific Information NI 6220 PCI/PXI-6220 Pinout Figure A-1 shows the pinout of the PCI/PXI-6220. Figure A-1. PCI/PXI-6220 Pinout 68 34 AI 0 (AI 0+) AI 8 (AI 0-) 67 33 AI GND AI 1 (AI 1+) 66 32 AI 9 (AI 1-) AI GND 65 31...
  • Page 160 Specifications—Refer to the NI 6220 Specifications for more detailed information about • the PCI/PXI-6220 device. Accessory and Cabling Options—Refer to the 68-Pin M Series Cables and Accessories • DAQ System Overview, for more information. section of Chapter 2, © National Instruments | A-3...
  • Page 161 Appendix A Module/Device-Specific Information NI 6221 (68-Pin) The following sections contain information about the PCI/PXI-6221, USB-6221 Screw Terminal, and USB-6221 BNC. PCI/PXI-6221 PCI/PXI-6221 Pinout Figure A-2 shows the pinout of the PCI/PXI-6221. A-4 | ni.com...

  • Page 162: Figure A-2. Pci/Pxi-6221 Pinout

    PFI 3/P1.3 +5 V PFI 4/P1.4 D GND PFI 13/P2.5 PFI 5/P1.5 PFI 15/P2.7 PFI 6/P1.6 PFI 7/P1.7 D GND PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 NC = No Connect © National Instruments | A-5...
  • Page 163 Appendix A Module/Device-Specific Information Table A-2. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 164: Figure A-3. Usb-6221 Screw Terminal Pinout

    CTR 0 GATE 83 (PFI 9) CTR 0 AUX 85 (PFI 10) CTR 0 OUT 89 (PFI 12) CTR 0 A 81 (PFI 8) CTR 0 Z 83 (PFI 9) CTR 0 B 85 (PFI 10) © National Instruments | A-7...
  • Page 165 Appendix A Module/Device-Specific Information Table A-3. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) CTR 1 SRC 76 (PFI 3) CTR 1 GATE 77 (PFI 4) CTR 1 AUX 87 (PFI 11) CTR 1 OUT 91 (PFI 13) CTR 1 A 76 (PFI 3) CTR 1 Z...

  • Page 166: Figure A-4. Usb-6221 Bnc Top Panel And Pinout

    M Series User Manual USB-6221 BNC USB-6221 BNC Pinout Figure A-4 shows the pinout of the USB-6221 BNC. Figure A-4. USB-6221 BNC Top Panel and Pinout © National Instruments | A-9...
  • Page 167 Appendix A Module/Device-Specific Information Table A-4. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Name CTR 0 SRC PFI 8 CTR 0 GATE PFI 9 CTR 0 AUX PFI 10 CTR 0 OUT PFI 12 CTR 0 A PFI 8 CTR 0 Z PFI 9 CTR 0 B...

  • Page 168: Figure A-5. Pci-6221 (37-Pin) Pinout

    CTR 0 AUX 33 (PFI 2) CTR 0 OUT 17 (PFI 6) CTR 0 A 13 (PFI 0) CTR 0 Z 32 (PFI 1) CTR 0 B 33 (PFI 2) CTR 1 SRC 15 (PFI 3) © National Instruments | A-11...
  • Page 169 Appendix A Module/Device-Specific Information Table A-5. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) CTR 1 GATE 34 (PFI 4) CTR 1 AUX 35 (PFI 5) CTR 1 OUT 36 (PFI 7) CTR 1 A 15 (PFI 3) CTR 1 Z 34 (PFI 4) CTR 1 B...

  • Page 170: Figure A-6. Pci/Pxi-6224 Pinout

    AI 25 (AI 17-) D GND PFI 12/P2.4 AI 17 (AI 17+) 33 67 AI GND D GND AI 24 (AI 16-) 34 68 AI 16 (AI 16+) PFI 14/P2.6 NC = No Connect NC = No Connect © National Instruments | A-13...
  • Page 171 Appendix A Module/Device-Specific Information Table A-6. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 172: Figure A-7. Pci/Pxi-6225 Pinout

    AI 26 (AI 18-) D GND PFI 12/P2.4 AI 17 (AI 17+) 33 67 AI 25 (AI 17-) D GND PFI 14/P2.6 34 68 AI 16 (AI 16+) AI 24 (AI 16-) NC = No Connect © National Instruments | A-15...
  • Page 173 Appendix A Module/Device-Specific Information Table A-7. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 174: Figure A-8. Usb-6225 Screw Terminal Pinout

    D GND AI 69 (AI 69+) PFI 5/P1.5 AI 78 (AI 70-) PFI 15/P2.7 AI 70 (AI 70+) PFI 6/P1.6 AI 79 (AI 71-) +5 V AI 71 (AI 71+) PFI 7/P1.7 NC = No Connect © National Instruments | A-17...
  • Page 175 Appendix A Module/Device-Specific Information Table A-8. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 113 (PFI 8) CTR 0 GATE 115 (PFI 9) CTR 0 AUX 117 (PFI 10) CTR 0 OUT 121 (PFI 12) CTR 0 A 113 (PFI 8) CTR 0 Z...

  • Page 176: Figure A-9. Usb-6225 Mass Termination Pinout

    AI 71 (AI 71+) D GND PFI 14/P2.6 NC = No Connect Table A-9. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) © National Instruments | A-19...
  • Page 177 Appendix A Module/Device-Specific Information Table A-9. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10)

  • Page 178: Figure A-10. Pci/Pxi-6229 Pinout

    AI 25 (AI 17-) D GND PFI 12/P2.4 AI 17 (AI 17+) 33 67 AI GND 34 68 AI 16 (AI 16+) D GND PFI 14/P2.6 AI 24 (AI 16-) NC = No Connect NC = No Connect © National Instruments | A-21...
  • Page 179 Appendix A Module/Device-Specific Information Table A-10. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 180: Figure A-11. Usb-6229 Screw Terminal Pinout

    P0.19 PFI 14/P2.6 P0.30 PFI 4/P1.4 P0.20 D GND D GND PFI 5/P1.5 P0.21 PFI 15/P2.7 P0.31 PFI 6/P1.6 P0.22 +5 V D GND PFI 7/P1.7 P0.23 NC = No Connect NC = No Connect © National Instruments | A-23...
  • Page 181 Appendix A Module/Device-Specific Information Table A-11. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 81 (PFI 8) CTR 0 GATE 83 (PFI 9) CTR 0 AUX 85 (PFI 10) CTR 0 OUT 89 (PFI 12) CTR 0 A 81 (PFI 8) CTR 0 Z...

  • Page 182: Figure A-12. Usb-6229 Bnc Top Panel And Pinout

    M Series User Manual USB-6229 BNC USB-6229 BNC Pinout Figure A-12 shows the pinout of the USB-6229 BNC. Figure A-12. USB-6229 BNC Top Panel and Pinout © National Instruments | A-25...
  • Page 183 Appendix A Module/Device-Specific Information Table A-12. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Name CTR 0 SRC PFI 8 CTR 0 GATE PFI 9 CTR 0 AUX PFI 10 CTR 0 OUT PFI 12 CTR 0 A PFI 8 CTR 0 Z PFI 9 CTR 0 B...

  • Page 184: Figure A-13. Pci/Pxi-6250 Pinout

    PFI 3/P1.3 +5 V PFI 4/P1.4 D GND PFI 13/P2.5 PFI 5/P1.5 PFI 15/P2.7 PFI 6/P1.6 PFI 7/P1.7 D GND PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 NC = No Connect © National Instruments | A-27...
  • Page 185 Appendix A Module/Device-Specific Information Table A-13. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 186: Figure A-14. Ni Pci/Pcie/Pxi/Pxie-6251 Pinout

    PFI 2/P1.2 D GND PFI 3/P1.3 +5 V PFI 4/P1.4 D GND PFI 13/P2.5 PFI 5/P1.5 PFI 15/P2.7 PFI 6/P1.6 PFI 7/P1.7 D GND PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 © National Instruments | A-29...
  • Page 187 Appendix A Module/Device-Specific Information Table A-14. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 188: Figure A-15. Usb-6251 Screw Terminal Pinout

    CTR 0 AUX 85 (PFI 10) CTR 0 OUT 89 (PFI 12) CTR 0 A 81 (PFI 8) CTR 0 Z 83 (PFI 9) CTR 0 B 85 (PFI 10) CTR 1 SRC 76 (PFI 3) © National Instruments | A-31...
  • Page 189 Appendix A Module/Device-Specific Information Table A-15. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) CTR 1 GATE 77 (PFI 4) CTR 1 AUX 87 (PFI 11) CTR 1 OUT 91 (PFI 13) CTR 1 A 76 (PFI 3) CTR 1 Z 77 (PFI 4) CTR 1 B...

  • Page 190: Figure A-16. Usb-6251 Bnc Top Panel And Pinout

    M Series User Manual USB-6251 BNC USB-6251 BNC Pinout Figure A-16 shows the pinout of the USB-6251 BNC. Figure A-16. USB-6251 BNC Top Panel and Pinout © National Instruments | A-33...
  • Page 191 Appendix A Module/Device-Specific Information Table A-16. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Name CTR 0 SRC PFI 8 CTR 0 GATE PFI 9 CTR 0 AUX PFI 10 CTR 0 OUT PFI 12 CTR 0 A PFI 8 CTR 0 Z PFI 9 CTR 0 B...

  • Page 192: Figure A-17. Usb-6251 Mass Termination Pinout

    PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 Table A-17. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) © National Instruments | A-35...
  • Page 193 Appendix A Module/Device-Specific Information Table A-17. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10) CTR 1 SRC...

  • Page 194: Figure A-18. Pci/Pxi-6254 Pinout

    AI GND AI 25 (AI 17–) AI 17 (AI 17+) AI GND D GND PFI 12/P2.4 D GND PFI 14/P2.6 AI 24 (AI 16–) AI 16 (AI 16+) NC = No Connect NC = No Connect © National Instruments | A-37...
  • Page 195 Appendix A Module/Device-Specific Information Table A-18. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 196: Figure A-19. Pci/Pxi-6255 Pinout

    AI 18 (AI 18+) AI 26 (AI 18–) D GND PFI 12/P2.4 AI 17 (AI 17+) AI 25 (AI 17–) D GND PFI 14/P2.6 AI 24 (AI 16–) AI 16 (AI 16+) NC = No Connect © National Instruments | A-39...
  • Page 197 Appendix A Module/Device-Specific Information Table A-19. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 198: Figure A-20. Usb-6255 Screw Terminal Pinout

    AI 77 (AI 69-) D GND AI 69 (AI 69+) PFI 5/P1.5 AI 78 (AI 70-) PFI 15/P2.7 AI 70 (AI 70+) PFI 6/P1.6 AI 79 (AI 71-) +5 V AI 71 (AI 71+) PFI 7/P1.7 © National Instruments | A-41...
  • Page 199 Appendix A Module/Device-Specific Information Table A-20. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 113 (PFI 8) CTR 0 GATE 115 (PFI 9) CTR 0 AUX 117 (PFI 10) CTR 0 OUT 121 (PFI 12) CTR 0 A 113 (PFI 8) CTR 0 Z...

  • Page 200: Figure A-21. Usb-6255 Mass Termination Pinout

    AI 79 (AI 71-) AI 71 (AI 71+) D GND PFI 14/P2.6 Table A-21. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) © National Instruments | A-43...
  • Page 201 Appendix A Module/Device-Specific Information Table A-21. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10) CTR 1 SRC...

  • Page 202: Figure A-22. Ni Pci/Pcie/Pxi/Pxie-6259 Pinout

    AI 18 (AI 28+) PFI 8/P2.0 AI GND PFI 9/P2.1 AI 25 (AI 17–) D GND PFI 12/P2.4 AI 17 (AI 17+) AI GND D GND PFI 14/P2.6 AI 24 (AI 16–) AI 16 (AI 16+) © National Instruments | A-45...
  • Page 203 Appendix A Module/Device-Specific Information Table A-22. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...

  • Page 204: Figure A-23. Usb-6259 Screw Terminal Pinout

    PFI 2/P1.2 P0.18 D GND D GND PFI 3/P1.3 P0.19 PFI 14/P2.6 P0.30 PFI 4/P1.4 P0.20 D GND D GND PFI 5/P1.5 P0.21 PFI 15/P2.7 P0.31 PFI 6/P1.6 P0.22 +5 V D GND PFI 7/P1.7 P0.23 © National Instruments | A-47...
  • Page 205 Appendix A Module/Device-Specific Information Table A-23. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 81 (PFI 8) CTR 0 GATE 83 (PFI 9) CTR 0 AUX 85 (PFI 10) CTR 0 OUT 89 (PFI 12) CTR 0 A 81 (PFI 8) CTR 0 Z...

  • Page 206: Figure A-24. Usb-6259 Bnc Top Panel And Pinout

    M Series User Manual USB-6259 BNC USB-6259 BNC Pinout Figure A-24 shows the pinout of the USB-6259 BNC. Figure A-24. USB-6259 BNC Top Panel and Pinout © National Instruments | A-49...
  • Page 207 Appendix A Module/Device-Specific Information Table A-24. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Name CTR 0 SRC PFI 8 CTR 0 GATE PFI 9 CTR 0 AUX PFI 10 CTR 0 OUT PFI 12 CTR 0 A PFI 8 CTR 0 Z PFI 9 CTR 0 B...
  • Page 208 PFI 12/P2.4 D GND P0.30 D GND PFI 14/P2.6 Table A-25. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) © National Instruments | A-51...
  • Page 209 Appendix A Module/Device-Specific Information Table A-25. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10)
  • Page 210 PFI 3/P1.3 +5 V PFI 4/P1.4 D GND PFI 13/P2.5 PFI 5/P1.5 PFI 15/P2.7 PFI 6/P1.6 PFI 7/P1.7 D GND PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 NC = No Connect © National Instruments | A-53...
  • Page 211 Appendix A Module/Device-Specific Information Table A-26. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...
  • Page 212 PFI 2/P1.2 D GND PFI 3/P1.3 +5 V PFI 4/P1.4 D GND PFI 13/P2.5 PFI 5/P1.5 PFI 15/P2.7 PFI 6/P1.6 PFI 7/P1.7 D GND PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 © National Instruments | A-55...
  • Page 213 Appendix A Module/Device-Specific Information Table A-27. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...
  • Page 214 CTR 0 AUX 85 (PFI 10) CTR 0 OUT 89 (PFI 12) CTR 0 A 81 (PFI 8) CTR 0 Z 83 (PFI 9) CTR 0 B 85 (PFI 10) CTR 1 SRC 76 (PFI 3) © National Instruments | A-57...
  • Page 215 Appendix A Module/Device-Specific Information Table A-28. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) CTR 1 GATE 77 (PFI 4) CTR 1 AUX 87 (PFI 11) CTR 1 OUT 91 (PFI 13) CTR 1 A 76 (PFI 3) CTR 1 Z 77 (PFI 4) CTR 1 B...
  • Page 216 PFI 8/P2.0 PFI 9/P2.1 D GND PFI 12/P2.4 D GND PFI 14/P2.6 Table A-29. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) © National Instruments | A-59...
  • Page 217 Appendix A Module/Device-Specific Information Table A-29. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10) CTR 1 SRC...
  • Page 218 NC = No Connect Table A-30. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) © National Instruments | A-61...
  • Page 219 Appendix A Module/Device-Specific Information Table A-30. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10) CTR 1 SRC 42 (PFI 3)
  • Page 220 PFI 9/P2.1 AI GND 32 66 AI 25 (AI 17–) D GND PFI 12/P2.4 AI 17 (AI 17+) 33 67 AI GND 34 68 AI 16 (AI 16+) D GND PFI 14/P2.6 AI 24 (AI 16–) © National Instruments | A-63...
  • Page 221 Appendix A Module/Device-Specific Information Table A-31. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z...
  • Page 222 PFI 2/P1.2 P0.18 D GND D GND PFI 3/P1.3 P0.19 PFI 14/P2.6 P0.30 PFI 4/P1.4 P0.20 D GND D GND PFI 5/P1.5 P0.21 PFI 15/P2.7 P0.31 PFI 6/P1.6 P0.22 +5 V D GND PFI 7/P1.7 P0.23 © National Instruments | A-65...
  • Page 223 Appendix A Module/Device-Specific Information Table A-32. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) CTR 0 SRC 81 (PFI 8) CTR 0 GATE 83 (PFI 9) CTR 0 AUX 85 (PFI 10) CTR 0 OUT 89 (PFI 12) CTR 0 A 81 (PFI 8) CTR 0 Z...
  • Page 224 PFI 12/P2.4 D GND P0.30 D GND PFI 14/P2.6 Table A-33. Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 SRC 37 (PFI 8) CTR 0 GATE 3 (PFI 9) © National Instruments | A-67...
  • Page 225 Appendix A Module/Device-Specific Information Table A-33. Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Connector 0 Pin Number (Name) CTR 0 AUX 45 (PFI 10) CTR 0 OUT 2 (PFI 12) CTR 0 A 37 (PFI 8) CTR 0 Z 3 (PFI 9) CTR 0 B 45 (PFI 10)
  • Page 226 Timing—Output timing refers to the timing parameters related to exporting signals • internal to the device to a terminal for external use. Figure B-1 is a simplified model of the M Series analog input timing engine. © National Instruments | B-1...
  • Page 227 Appendix B Timing Diagrams Figure B-1. M Series Analog Input Timing Engine POUT Selected Reference Trigger Reference Trigger Terminal Terminal POUT Start Trigger Terminal Terminal Selected Start Trigger POUT RTSI Selected Pause Trigger Terminal Pause Trigger SI Start (and Other Counters, Terminal and Such of Timer Core) Sample Clock Timebase...
  • Page 228 Input timing refers to the delays involved in importing external signals to be used as triggers or clocks in the AI timing engine. Figures B-2 and B-3 and Table B-1 describe the insertion delays for external signals. © National Instruments | B-3...
  • Page 229 Appendix B Timing Diagrams Figure B-2. Input Timing and the Analog Input Timing Engine Selected Reference Trigger Reference Trigger Terminal Terminal Start Trigger Terminal Terminal Selected Start Trigger RTSI Selected Pause Trigger Terminal Pause Trigger SI Start Terminal Sample Clock Timebase Counter Block Sync Sample Clock Timebase...
  • Page 230 The source for Convert Clock Timebase and Sample Clock Timebase is the internal signal bus, _i. The timing of this signal is described in relation to this common point. The Convert Clock Timebase and Sample Clock Timebase can be asynchronous from each other. © National Instruments | B-5...
  • Page 231 Appendix B Timing Diagrams Figure B-4. AI Timing Clocks and the Analog Input Timing Engine Selected Reference Trigger Reference Trigger Terminal Terminal Start Trigger Terminal Terminal Selected Start Trigger RTSI Pause Trigger Pause Trigger Terminal Pause Trigger SI Start Terminal Sample Clock Timebase Counter Block...
  • Page 232 Convert Clock Timebase and the Sync Convert Clock Timebase is an asynchronous delay. Whether the SI2 counter is used or not, the timing parameters in the generation of Convert Clock are the same starting at the Convert Clock Timebase signal. © National Instruments | B-7...
  • Page 233 Appendix B Timing Diagrams Figure B-6. Convert Clock and the Analog Input Timing Engine Selected Reference Trigger Reference Trigger Terminal Terminal Start Trigger Terminal Terminal Selected Start Trigger RTSI Selected Pause Trigger Terminal Pause Trigger SI Start Terminal Sample Clock Timebase Counter Block Sync Sample Clock Timebase...
  • Page 234 Sample Clock (beginning of a sample). Once the Sample Clock Timebase domain has received a valid Start Trigger, the AI timing engine is ready to begin generating Sample Clocks. © National Instruments | B-9...
  • Page 235 Appendix B Timing Diagrams Figure B-9. Convert Clock Timebase Timing and the Analog Input Timing Engine Selected Reference Trigger Reference Trigger Terminal Terminal POUT Start Trigger Terminal Terminal RTSI Selected Pause Trigger Terminal Pause Trigger SI Start Terminal Sample Clock Timebase Counter Block Sync Sample Clock Timebase...
  • Page 236 Selected Pause Trigger Terminal SI Start Pause Trigger Terminal Sample Clock Timebase Counter Block Sync Sample Clock Timebase Terminal SI_TC p_AI_Convert SI2_TC Convert Clock Timebase Counter Block Sync Convert Clock Timebase Start Selected Sample Clock Terminal Terminal © National Instruments | B-11...
  • Page 237 Appendix B Timing Diagrams Figure B-12. Sample Clock Timebase Timing Diagram Selected Start Trigger Sync Sample Clock Timebase SI Start Table B-6. Sample Clock Timebase Timing Time Description Line Min (ns) Max (ns) Delay to Selected Start Trigger RTSI STAR Selected Start Trigger —...
  • Page 238 Terminal SI_TC p_AI_Convert SI2_TC Convert Clock Timebase Counter Block Sync Convert Clock Timebase Start Selected Sample Clock Terminal Terminal Figure B-14. Reference Trigger Timing Diagram Selected Reference Trigger Sync Convert Clock Timebase Reference Trigger POUT © National Instruments | B-13...
  • Page 239 Appendix B Timing Diagrams Table B-7. Reference Trigger Timing Time Description Line Min (ns) Max (ns) Delay to the Selected Reference Trigger RTSI STAR Selected Reference Trigger — — Setup (to Sync Convert Clock Timebase) Selected Reference Trigger — — Hold (to Sync Convert Clock Timebase) Sync Convert Clock Timebase...
  • Page 240 Terminal SI_TC p_AI_Convert SI2_TC Convert Clock Timebase Counter Block Sync Convert Clock Timebase Start Selected Sample Clock Terminal Terminal Figure B-16. Sample Clock Timing Diagram Selected Sample Clock Sync Convert Clock Timebase Sample Clock POUT © National Instruments | B-15...
  • Page 241 Appendix B Timing Diagrams Table B-8. Sample Clock Timing Time Description Line Min (ns) Max (ns) Delay to Selected Sample Clock RTSI STAR Selected Sample Clock Setup time — — (to Sync Convert Clock Timebase) Selected Sample Clock Hold time —...
  • Page 242 Terminal SI_TC p_AI_Convert SI2_TC Convert Clock Timebase Counter Block Sync Convert Clock Timebase Start Selected Sample Clock Terminal Terminal Figure B-19. Pause Trigger Timing Diagram Selected Pause Trigger Sync Convert Clock Timebase Pause Trigger POUT © National Instruments | B-17...
  • Page 243 Appendix B Timing Diagrams Table B-10. Pause Trigger Timing Time Description Line Min (ns) Max (ns) _i to Selected Gate RTSI STAR Selected Pause Trigger Setup Time — — (to Sync Convert Clock Timebase) Hold (Sync Convert Clock Timebase) — —...
  • Page 244 Sync Convert Clock Timebase Start POUT Selected Sample Clock Terminal Terminal Figure B-21. Output Timing Diagram POUT Terminal Table B-11. Output Timing Edge Line Min (ns) Max (ns) Rising Edge 25.7 RTSI 14.0 Falling Edge 25.9 RTSI 13.9 © National Instruments | B-19...
  • Page 245 Appendix B Timing Diagrams Analog Output Timing Diagrams The analog output timing can be broken into the following three sections: Input Timing—The timing for external signals to enter the M Series device and be available • on the internal signal buses. Internal Analog Output Timing—The timing specifications of the analog output unit itself, •...
  • Page 246 The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a given condition (maximum or minimum timing). This difference can be useful when two external signals will be used together and the relative timing between the signals is important. © National Instruments | B-21...
  • Page 247 Appendix B Timing Diagrams Internal Analog Output Timing The analog output timer has two internal clocks that are referenced—Sample Clock Timebase and Sync Sample Clock Timebase. How they are generated depends on how the analog output timer is configured. If the analog output timing engine is configured to operate with an external Sample Clock, analog output internal clock timing can be derived from Table B-13.
  • Page 248 Min (ns) Max (ns) Setup — Hold — Pause Trigger The analog output Pause Trigger can be used to pause an ongoing generation. It is received on the rising edge of Sync Sample Clock Timebase. © National Instruments | B-23...
  • Page 249 Appendix B Timing Diagrams Figure B-28. Pause Trigger Input Delay Path Signal_i To Internal Logic Logic Selected Pause Trigger Sync Sample Clock Timebase Figure B-29. Pause Trigger Timing Diagram Signal_i Selected Pause Trigger Sync Sample Clock Timebase Table B-17. Pause Trigger Timing from Signal_i to Selected Pause Trigger Time From Min (ns)
  • Page 250 Start Trigger—As an output, the Start Trigger is routed as an asynchronous pulse. The • actual signal that gets routed is the Selected Start Trigger signal, so there is no synchronous delay involved. © National Instruments | B-25...
  • Page 251 Appendix B Timing Diagrams Figure B-31. Start Trigger Path Routing Logic RTSI, PFI Selected Start Trigger To Internal Logic Sync Sample Clock Timebase Figure B-32. Start Trigger Output Delay Timing Diagram Selected Start Trigger PFI/RTSI Terminal Table B-19. Start Trigger Output Delay Timing Time From Min (ns)
  • Page 252 Figure B-36. Sample Clock Delay Timing Diagram Sample Clock Timebase RTSI/PFI Terminal Table B-21. Sample Clock Delay Timing Time From Min (ns) Max (ns) AO Sample Clock 10.7 31.1 34.3 AO Sample Clock RTSI 21.3 21.7 © National Instruments | B-27...
  • Page 253 Appendix B Timing Diagrams Digital I/O Timing Diagrams This section describes the timing delays and requirements of digital waveform acquisitions and digital waveform generations. Digital Waveform Acquisition Timing To describe digital waveform acquisition timing delays and requirements, refer to the circuitry shown in Figure B-37.
  • Page 254 PFI, RTSI, or When used as DI 12.0 — PXI_STAR Sample Clock minimum pulse width Setup time from P0_i — — to DI Sample Clock Hold time from DI — — Sample Clock to P0_i © National Instruments | B-29...
  • Page 255 Appendix B Timing Diagrams Digital Waveform Generation Timing To describe digital waveform generation timing delays and requirements, we model the circuitry as shown in Figure B-39. In the figure, P0, PFI, RTSI, and PXI_STAR represent signals at connector pins of the M Series device. The other named signals represent internal signals. Figure B-39.
  • Page 256 Figure B-41. In the figure, PFI, RTSI, and PXI_STAR represent signals at connectors pins of the M Series device. The other named signals represent internal signals. © National Instruments | B-31...
  • Page 257 Appendix B Timing Diagrams Figure B-41. Counter/Timer Circuitry PFI, RTSI, PFI_i, RTSI_i, or PXI_STAR or PXI_STAR_i PFI, RTSI, or PXI_STAR (Counter n Gate) Count_Enable Out_o PFI, RTSI, Selected_Gate Other Internal Gate 32-Bit or PXI_STAR Signals Logic Counter (Counter n Internal Output) PFI, RTSI, Selected_Source 80 MHz Timebase...
  • Page 258 PXI_STAR_i Selected_Gate Table B-27. Selected Gate Delays Timing Time From Min (ns) Max (ns) PFI_i, RTSI_i, Selected Gate PXI_STAR_i, or any internal signal Figure B-44. Selected Source Delays Timing Diagram PFI_i, RTSI_i, or PXI_STAR_i Selected_Source © National Instruments | B-33...
  • Page 259 Appendix B Timing Diagrams Table B-28. Selected Source Delays Timing Time From Min (ns) Max (ns) PFI_i, RTSI_i, PXI_STAR_i, or any Selected 21.0 internal signal Source 20 MHz Timebase Selected Source 100 kHz Timebase Selected Source 80 MHz Timebase Selected Source PXI_CLK10 Selected...
  • Page 260 Counter n Source Table B-30. Counter n Source Timing Synchronization Time Description Mode Min (ns) Max (ns) Counter n Source Period 80 MHz Source 12.5 — Other Internal 25.0 — Source External Source 50.0 — © National Instruments | B-35...
  • Page 261 Appendix B Timing Diagrams Table B-30. Counter n Source Timing (Continued) Synchronization Time Description Mode Min (ns) Max (ns) Counter n Source Pulse 80 MHz Source — Width Other Internal 12.5 — Source External Source 16.0 — The times in this table are measured at the pin of the M Series device. For example, t specifies the minimum period of a signal driving a PFI, RTSI, or PXI_STAR pin when that signal is internally routed to Counter n Source.
  • Page 262 Figure B-49. DAQ-STC2 Internal Block Setup and Hold Requirements Timing Diagram Count_Enable Selected_Source Table B-33. DAQ-STC2 Internal Block Setup and Hold Requirements Timing Time Parameter Min (ns) Max (ns) Setup — Hold — © National Instruments | B-37...
  • Page 263 Appendix B Timing Diagrams Example of the General Case Calculate the setup and hold time requirements when the Gate and Source come from PFI lines and the Gate is used in level mode. Note This example shows how we determine the setup and hold times for the PFI to PFI example above (first case) using level gating.
  • Page 264 In NI-DAQmx, the counter/timers use level gating mode for the following measurements: • Edge counting • Pulse width measurements • Two-signal edge separation measurements All other measurements use edge gating mode. © National Instruments | B-39...
  • Page 265 Appendix B Timing Diagrams Quadrature and Two Pulse Encoder Timing Counter n A, Counter n B, and Counter n Z, described in the Counter n A, Counter n B, and Counter n Z Signals section of Chapter 7, Counters, are used in position measurements using quadrature encoder or two-pulse encoder counting modes.
  • Page 266 Table B-36. Generating Different Clocks from the Onboard 80 MHz Oscillator Time From Min (ns) Max (ns) Onboard 80 MHz 80 MHz Timebase Oscillator 80 MHz Timebase 20 MHz Timebase 80 MHz Timebase 100 kHz Timebase © National Instruments | B-41...
  • Page 267 Appendix B Timing Diagrams Table B-37 shows delays for generating different clocks using an External Reference Clock and the PLL. Figure B-53. Generating Different Clocks Using an External Reference Clock and the PLL RTSI <0..7> STAR_TRIG PXI_CLK10 (Reference Clock) 80 MHz Timebase (PLL) 20 MHz Timebase (PLL) Table B-37.
  • Page 268 Troubleshooting This section contains common questions about M Series devices. If your questions are not answered here, refer to the National Instruments KnowledgeBase at ni.com/kb Analog Input I am seeing crosstalk, or ghost voltages, when sampling multiple channels. What does this...
  • Page 269 Appendix C Troubleshooting How can I use the AI Sample Clock and AI Convert Clock signals on an M Series device to sample the AI channel(s)? M Series devices use AI Sample Clock (ai/SampleClock) and AI Convert Clock (ai/ConvertClock) to perform interval sampling. As Figure C-1 shows, AI Sample Clock controls the sample period, which is determined by the following equation: 1/sample period = sample rate Figure C-1.
  • Page 270 Series, lists issues encountered when upgrading Appendix D, from E Series to M Series devices. Customers also can refer to NI’s KnowledgeBase at for more updated ni.com/kb troubleshooting tips and answers to frequently asked questions about M Series devices. © National Instruments | C-3...
  • Page 271 The pinout of Connector 0 of 68-pin M Series devices is similar to the pinout of 68-pin E Series devices. On M Series devices, some terminals have enhanced functionality or other slight differences. Table D-1 compares the two pinouts. © National Instruments | D-1...
  • Page 272 Appendix D Upgrading from E Series to M Series Table D-1. M Series and E Series Device Pinout Comparison M Series E Series Signal Signal Differences FREQ OUT PFI 14/P2.6 E Series devices drive each of these terminals with one particular internal timing signal.
  • Page 273 On E Series devices, this is one of the D GND terminals. On M Series devices, this is the PFI 15/P2.7 terminal. In NI-DAQmx, National Instruments has revised terminal names so they are easier to understand and more consistent among National Instruments hardware and software products. This column shows the NI-DAQmx terminal names (Traditional NI-DAQ (Legacy) terminal names are shown in parentheses).
  • Page 274 Appendix D Upgrading from E Series to M Series More Information about Upgrading to M Series The following documents will help you overcome typical hurdles in upgrading from E Series to M Series devices: Major Differences Between E Series and M Series DAQ Devices KnowledgeBase lists the •...
  • Page 275 The B/E/M/S/X Series Calibration Procedure contains information for calibrating your multifunction I/O device. Go to ni.com/manuals NI-DAQmx for Windows The NI-DAQmx Readme lists which devices, ADEs, and NI application software are supported by this version of NI-DAQmx. © National Instruments | E-1...
  • Page 276 The NI-DAQmx Base C Reference Help contains C reference and general information about measurement concepts. Note All NI-DAQmx Base documentation for Linux is installed at /usr/local/natinst/nidaqmxbase/documentation Note All NI-DAQmx Base documentation for Mac OS X is installed at /Applications/National Instruments/NI-DAQmx Base/ documentation E-2 | ni.com...
  • Page 277 If you program your NI-DAQmx-supported device in Measurement Studio using Visual C# or Visual Basic .NET, you can interactively create channels and tasks by launching the DAQ Assistant from MAX or from within Visual Studio. You can use Measurement Studio to generate © National Instruments | E-3...
  • Page 278 Select Start»All Programs»National Instruments»NI-DAQmx» NI-DAQmx Help. The NI-DAQmx C Reference Help describes the NI-DAQmx Library functions, which you can use with National Instruments data acquisition devices to develop instrumentation, acquisition, and control applications. Select Start»All Programs»National Instruments»NI-DAQmx» Text-Based Code Support»NI-DAQmx C Reference Help.
  • Page 279 Reader 7.0 or later (PDF 1.6 or later) installed to view the PDFs. Refer to the Adobe Systems Incorporated website at to download Adobe Reader. Refer to the National www.adobe.com Instruments Product Manuals Library at for updated documentation ni.com/manuals resources. © National Instruments | E-5...
  • Page 280 System Integration—If you have time constraints, limited in-house technical resources, or • other project challenges, National Instruments Alliance Partner members can help. To learn more, call your local NI office or visit ni.com/alliance © National Instruments | F-1...
  • Page 281 Appendix F NI Services Training and Certification—The NI training and certification program is the most • effective way to increase application development proficiency and productivity. Visit for more information. ni.com/training – The Skills Guide assists you in identifying the proficiency requirements of your current application and gives you options for obtaining those skills consistent with your time and budget constraints and personal learning preferences.
  • Page 282 PCI-6221 (37-pin), A-12 ai/SampleClockTimebase, 4-25 USB-6221 BNC, A-10 ai/StartTrigger, 4-29 USB-6221 Screw Terminal, A-8 analog USB-6225 Mass Termination, A-20 comparison event, routing, 11-3 USB-6225 Screw Terminal, A-18 comparison event, signal, 11-3 USB-6229 BNC, A-26 edge triggering, 11-3 © National Instruments | I-1...
  • Page 283 Index trigger actions, 11-3 getting started with applications in trigger types, 11-3 software, 5-10 triggering, 11-2 glitches on the output signal, 5-3 analog edge triggering offset, 5-2 with hysteresis, 11-4 reference selection, 5-2 analog input, 4-1 signals, 5-6 channels, 11-2 AO Pause Trigger, 5-7 charge injection, C-1 AO Sample Clock, 5-8...
  • Page 284 USB-6225 Mass Termination, A-20 connector USB-6251 Mass Termination, A-36 information, 3-1 USB-6255 Mass Termination, A-44 PCI/PCIe/PXI/PXIe-6251 pinout, A-29 USB-6259 Mass Termination, A-52 PCI/PCIe/PXI/PXIe-6259 pinout, A-45 USB-6281 Mass Termination, A-60 PCI/PXI-6220 pinout, A-2 USB-6289 Mass Termination, A-68 © National Instruments | I-3...
  • Page 285 Index PCI/PXI-6221 (68-pin) pinout, A-4 counter PCI/PXI-6224 pinout, A-13 input and output, 7-28 PCI/PXI-6225 pinout, A-15 output applications, 7-19 PCI/PXI-6229 pinout, A-21 terminals, default, 7-28 Counter n A signal, 7-27 PCI/PXI-6250 pinout, A-27 Counter n Aux signal, 7-26 PCI/PXI-6254 pinout, A-37 Counter n B signal, 7-27 PCI/PXI-6255 pinout, A-39 Counter n Gate signal, 7-25...
  • Page 286 NI 6250, A-27 timing diagrams, B-28 NI 6251, A-29 triggering, 11-1 NI 6254, A-37 waveform acquisition, 6-3 NI 6255, A-39 waveform triggering, 6-2 NI 6259, A-45 digital routing, 9-1 NI 6280, A-53 NI 6281, A-55 © National Instruments | I-5...
  • Page 287 Index digital signals encoding Change Detection Event, 6-7 X1, 7-15 connecting, 6-8 X2, 7-15 DI Sample Clock, 6-3 X4, 7-15 DO Sample Clock, 6-4 equivalent time sampling, 7-23 digital source, triggering, 11-1 example programs, E-1 digital waveform exporting timing output signals using PFI acquisition, 6-3 terminals, 8-2 generation, 6-4...
  • Page 288 USB-6251 Screw Terminal pinout, A-31 ground-referenced signal sources USB-6255 Mass Termination connecting, 4-17 pinout, A-43 description, 4-17 USB-6255 Screw Terminal pinout, A-41 using in differential mode, 4-19 USB-6259 BNC pinout, A-49 using in NRSE mode, 4-20 © National Instruments | I-7...
  • Page 289 Index USB-6259 Mass Termination USB-6251 Screw Terminal, A-32 pinout, A-51 USB-6255 Mass Termination, A-44 USB-6259 Screw Terminal pinout, A-47 USB-6255 Screw Terminal, A-42 USB-6281 Mass Termination USB-6259 BNC, A-50 pinout, A-59 USB-6259 Mass Termination, A-52 USB-6281 Screw Terminal pinout, A-57 USB-6259 Screw Terminal, A-48 USB-6289 Mass Termination USB-6281 Mass Termination, A-60...
  • Page 290 A-36 sources, 4-20 NI 6254, A-37 when to use with floating signal accessory options, A-38 sources, 4-12 cabling options, A-38 when to use with ground-referenced pinout, A-37 signal sources, 4-18 specifications, A-38 © National Instruments | I-9...
  • Page 291 PCI-6254, A-37 accessory options, A-46 PCI-6255, A-39 cabling options, A-46 PCI-6259, A-45 pinout, A-45 PCI-6280, A-53 specifications, A-46 PCI-6281, A-55 PCI/PXI-6221 (68-pin) PCI-6284, A-61 accessory options, A-6, A-12 PCIe-6251, A-29 cabling options, A-6, A-12 PCIe-6259, A-45 pinout, A-4 period measurement, 7-5...
  • Page 292 USB-6251 Mass Termination, A-35 and PXI, 10-3 USB-6251 Screw Terminal, A-31 chassis compatibility, 10-3 USB-6255 Mass Termination, A-43 PXI_CLK10, 9-8 USB-6255 Screw Terminal, A-41 PXI_STAR USB-6259 BNC, A-49 filters, 9-8 USB-6259 Mass Termination, A-51 trigger, 9-8 © National Instruments | I-11...
  • Page 293 Index PXI-6220, A-2 RSE connections PXI-6221, A-4 using with floating signal sources, 4-17 PXI-6224, A-13 when to use with floating signal PXI-6225, A-15 sources, 4-13 PXI-6229, A-21 when to use with ground-referenced PXI-6250, A-27 signal sources, 4-19 PXI-6251, A-29 RTSI, 9-4 PXI-6254, A-37 connector pinout, 3-7, 9-4 PXI-6255, A-39...
  • Page 294 USB-6251 Mass Termination, A-36 simple pulse generation, 7-19 USB-6251 Screw Terminal, A-32 single USB-6255 Mass Termination, A-44 period measurement, 7-5 USB-6255 Screw Terminal, A-42 point edge counting, 7-2 USB-6259 BNC, A-50 pulse generation, 7-19 USB-6259 Mass Termination, A-52 © National Instruments | I-13...
  • Page 295 Index USB-6259 Screw Terminal, A-48 analog output Pause Trigger, B-26 USB-6281 Mass Termination, A-60 analog output pause trigger, B-23 USB-6281 Screw Terminal, A-58 analog output signal definitions, B-20 USB-6289 Mass Termination, A-68 analog output Start trigger, B-23 USB-6289 Screw Terminal, A-66 analog output timing Start trigger, B-25 start clock generation, B-41...
  • Page 296 A-24, A-32 pinout, A-9 USB cable strain relief, 1-8, 1-12 USB cable strain relief, 1-8 USB-6251 BNC USB-6221 Mass Termination cable management, 1-8 USB cable strain relief, 1-8 fuse replacement, A-34 LED patterns, A-34 © National Instruments | I-15...
  • Page 297 Index pinout, A-33 USB-6259 Mass Termination specifications, A-34 accessory options, A-52 USB cable strain relief, 1-8 cabling options, A-52 USB-6251 Mass Termination fuse replacement, A-52 accessory options, A-36 LED patterns, A-52 cabling options, A-36 pinout, A-51 fuse replacement, A-36 specifications, A-52 LED patterns, A-36 USB cable strain relief, 1-8, 1-12 pinout, A-35...
  • Page 298 9-6 short high-quality cabling, 4-7 the disk drive power connector (PCI Express), 1-5 waveform generation digital, 6-4 signals, 5-6 triggering, 6-2 X1 encoding, 7-15 X2 encoding, 7-15 X4 encoding, 7-15 © National Instruments | I-17...

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