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Appendix B
Timing Diagrams
Digital Waveform Generation Timing
To describe digital waveform generation timing delays and requirements, we model the circuitry
as shown in Figure B-39. In the figure, P0, PFI, RTSI, and PXI_STAR represent signals at
connector pins of the M Series device. The other named signals represent internal signals.
Figure B-39. Digital Waveform Generation Timing Circuitry
PFI, RTSI,
or PXI_STAR
Figure B-40 and Tables B-24 and B-25 describe the digital waveform generation timing delays
and requirements. Your inputs must meet the requirements to ensure proper behavior.
Figure B-40. Digital Waveform Acquisition Timing Delays
PFI, RTSI,
or PXI_STAR
PFI_i, RTSI_i,
or PXI_STAR_i
DO Sample Clock
PFI (Output)
Time
*
t
PFI
12
RTSI
PXI_STAR
t
PFI_i, RTSI_i,
13
PXI_STAR_i, or other
internal signal
B-30 | ni.com
PFI_i, RTSI_i,
or PXI_STAR_i
Other Internal
Signals
t
12
t
13
P0
Table B-24. DO Timing Delays
From
PFI_i
RTSI_i
PXI_STAR_i
DO Sample
Clock
DO Waveform
DO Sample
Generation FIFO
Clock
t
10
t
t
11
11
t
12
t
13
t
14
t
t
15
16
To
Min (ns)
5.2
2.0
P0
PFI (Output)
Max (ns)
6.2
18.2
2.5
5.0
1.5
3.5
3.5
9.5
22.0
6.0
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