National Instruments PXI-6289 User Manual page 241

Appendix B Timing Diagrams
Time
t Delay to Selected Sample Clock
27
t Selected Sample Clock Setup time
28
(to Sync Convert Clock Timebase)
t Selected Sample Clock Hold time
29
(to Sync Convert Clock Timebase)
t Sync Convert Clock Timebase to Sample
30
Clock
t Sample Clock to POUT
31
The AI timing engine also can export a signal related to the Sample Clock called
AI_Sample_In_Progress. This signal asserts with the Sample Clock and stays asserted until after
the last convert of the sample. It is useful for external simultaneous sample and hold signal
conditioning.
Figure B-17. AI_Sample_In_Progress Timing Diagram
Sample Clock
Convert Clock
POUT
Time
t Sample Clock to POUT as
32
leading edge
of AI_Sample_In_Progress
t Convert Clock to POUT as
33
trailing edge
of AI_Sample_In_Progress
B-16 | ni.com
Table B-8. Sample Clock Timing
Description
t
32
Table B-9. AI_Sample_In_Progress Timing
Description
Line
PFI
RTSI
STAR
—
—
—
PFI
RTSI
t
33
Line Min (ns)
PFI 3.4
RTSI 4.2
PFI 5.4
RTSI 6.2
Min (ns) Max (ns)
3.5 8.9
3.4 8.6
2.8 5.9
1.5 —
0 —
2.4 5.8
2.4 5.5
3.2 6.8
Max (ns)
8.0
9.2
12.4
13.6