National Instruments PXI-6289 User Manual page 249

Appendix B Timing Diagrams
Signal_i
Sync Sample Clock Timebase
Sync Sample Clock Timebase
Table B-17. Pause Trigger Timing from Signal_i to Selected Pause Trigger
Time
t Signal_i
9
Time
t
10
t
11
Input Timing Verification
Consider an application that uses an external trigger and an external clock. The trigger and clock
signals are routed to an internal D flip-flop (DFF). To ensure that the trigger is sampled on a
particular clock edge, the setup and hold times of the internal DFF must be met:
• Recall that a "terminal" is a PFI pin, RTSI pin, or PXI_Star pin.
• Let TriggerDelay be the delay from the trigger terminal to the DFF.
• Let ClockDelay be the delay from the clock terminal to the DFF.
• Let DFF and DFF
Setup
• Let External
Setup
the terminals.
B-24 | ni.com
Figure B-28. Pause Trigger Input Delay Path
Logic
Selected Pause
Trigger
Figure B-29. Pause Trigger Timing Diagram
Signal_i
Selected Pause Trigger
From
Selected Pause Trigger
Table B-18. Pause Trigger Setup and Hold Timing
Parameter
Setup
Hold
be the setup and hold time of the DFF.
Hold
and External be the setup and hold time of the trigger to the clock at
Hold
D Q
t
9
t
9
t
t
10
11
To Min (ns)
Min (ns)
1.5
0
To Internal Logic
t
10
Max (ns)
1.7 7.8
Max (ns)
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