National Instruments PXI-6289 User Manual page 261

Appendix B Timing Diagrams
Time
Counter n Source Pulse
t
6
Width
*
The times in this table are measured at the pin of the M Series device. For example, t
minimum period of a signal driving a PFI, RTSI, or PXI_STAR pin when that signal is internally routed
to Counter n Source.
Gate Pulse Width
Figure B-47 and Table B-31 show the timing requirements for Counter n Gate. The requirements
depend on the gating mode.
Figure B-47. Counter n Gate Pulse Width Timing Diagram
Counter n Gate
Time Description
Counter n Gate Pulse
t
7
Width
Counter n Gate Pulse
Width
*
The times in this table are measured at the pin of the M Series device. That is, t
pulse width of a signal driving a PFI, RTSI, or PXI_STAR pin when that signal is internally routed to
Counter n Gate.
Gate to Source Setup and Hold
The counter can be modeled as a set of flip flops where the D input is Count Enable and the clock
input is Selected Source, as shown in Figure B-41. This section shows the setup and hold
requirements for two different cases:
A PFI pin drives Counter n Source and a different PFI pin drives Counter n Gate
•
• The general case (all other combinations of signals driving Source and Gate)
B-36 | ni.com
Table B-30. Counter n Source Timing (Continued)
Description
Table B-31. Counter n Gate Pulse Width Timing
Edge
Level
Synchronization
Mode
80 MHz Source
Other Internal
Source
External Source
t
7
t
7
Gating Mode
One Source Period
*
Min (ns)
6.2
12.5
16.0
specifies the
5
*
Min (ns) Max (ns)
12.0
specifies the minimum
7
Max (ns)
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