National Instruments PXI-6289 User Manual page 267

Appendix B Timing Diagrams
Table B-37 shows delays for generating different clocks using an External Reference Clock and
the PLL.
Figure B-53. Generating Different Clocks Using an External Reference Clock and the PLL
RTSI <0..7>
STAR_TRIG
PXI_CLK10
(Reference Clock)
80 MHz Timebase (PLL)
20 MHz Timebase (PLL)
Table B-37. Generating Different Clocks Using an External Reference Clock and the PLL
Time
t 80 MHz Timebase
4
t The source of the external
5
reference clock
(RTSI <0..7>, STAR_TRIG, PX
I_CLK10)
B-42 | ni.com
t
5
t
4
From To
20 MHz Timebase
80 MHz Timebase
(through PLL_OUT)
Min (ns) Max (ns)
1.5 5.0
1.0 5.5