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The A/D converter will convert one sample when you write to the
register Write BASE+0 with any value. User can check the A/D FIFO
status (A/D_F/E on register Read BASE+8) to make sure if the data is
ready to be received.
These two bytes in Read BASE+0 hold the result of A/D conversion
data.
The 12 bits of data from the A/D conversion are stored in bit 0 to bit
11, bit 12 to 14 hold the A/D channel number and bit 15 holds the
trigger event flag.
Table D-2: Register for channel number and A/D data
B
a
e s
A
d
. d
5 1
4 1
0
R
A
F
C
H
2
AD0
AD11
the most significant bit (MSB) of A/D data.
CH2 ~ CH0 hold the A/D channel number from which the data is
received.
CH2
MSB.
CH0
LSB.
Note:
A/D channel number specifies the channel from which data is derived.
CH2 is the MSB and CH0 is the LSB. For channel scan, there should
have 4 channel codes, specifically from CH0 to CH3. Because we have
not enough address space, bit 15 is used for other purposes instead for
CH3, which is hence not available..
The trigger flag indicates whether a trigger event has happened during
A/D conversion process.
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3 1
2 1
1 1
0 1
9
C
h
C
H
1
C
H
0
A
D
1 1
A
D
0 1
A
D
the least significant bit (LSB) of A/D data.
8
7
6
5
n a
e n
a l
d n
A
D /
a d
a t
9
A
D
8
A
D
7
A
D
6
A
D
5
– 83 –
PCI-1712/1712L User's Manual
APPENDIX D
4
3
2
1
0
A
D
4
A
D
3
A
D
2
A
D
1
A
D
0
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