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APPENDIX D
B
a
e s
A
d
. d
5 1
4 1
W
0 1
R
W
2 1
R
W
4 1
R
W
6 1
R
This counter chip 82C54 includes three counters use for special
purpose. Counter 0 is used as D/A counter to produce D/A output
pacer clock. Counter 1 is used as A/D counter to produce A/D pacer
clock. Counter 2 is used as DMA counter. Counter 0 and counter 1
should set in 82C54 mode 3 or mode 2 to produce clock. Counter 1 set
in mode 0 to count number of data. For detailed information, Intel(r)
82C54 User's Manual is available by accessing the following path on
CD-ROM:
\Document\Intel 82C54 manual.pdf
PCI-1712/1712L User's Manual
Table D-13: Register for 82C54 counter chip 0
3 1
2 1
1 1
0 1
9
– 94 –
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8
7
6
5
D
A /
o c
n u
r e t
0
D
7
D
6
D
5
D
A /
o c
n u
r e t
0
D
7
D
6
D
5
A
D /
o c
n u
r e t
1
D
7
D
6
D
5
A
D /
o c
n u
r e t
1
D
7
D
6
D
5
D
M
A
o c
n u
r e t
2
D
7
D
6
D
5
D
M
A
o c
n u
r e t
2
D
7
D
6
D
5
C
o
n u
r e t
c
n o
r t
l o
D
7
D
6
D
5
C
o
n u
r e t
c
n o
r t
l o
D
7
D
6
D
5
4
3
2
1
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
D
4
D
3
D
2
D
1
D
0
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