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APPENDIX D
B
a
e s
A
d
. d
5 1
4 1
W
2
A
R
D
O I
_
C
1
0
0
1
1
When all digital I/O channels are set as output channels, users can
confirm the data output status by reading back from digital input data
registers.
B
a
e s
A
d
. d
5 1
4 1
2
C
W
PCI-1712/1712L User's Manual
DI0 is the least significant bit (LSB) of the digital input data.
DI15 is the most significant bit (MSB) of the digital input
data.
Table D-20: Register for digital I/O configuration
3 1
2 1
1 1
0 1
D
g i
a t i
D
g i
a t i
Table D-21: Register for digital I/O configuration
D
O I
_
C
0
i H
h g
0
1
0
1
Table D-22: Register for calibration command
3 1
2 1
1 1
0 1
C
i l a
r b
C
M
3
C
M
2
C
– 100 –
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9
8
7
6
5
I l
O /
o c
f n
g i
r u
i t a
n o
r
g e
s i
r e t
I l
O /
o c
f n
g i
r u
i t a
n o
r
g e
s i
r e t
M
a e
i n
g n
B
y
e t
(
t i b
5 1
o t
) 8
O
u
p t
t u
O
u
p t
t u
I
p n
t u
I
p n
t u
—
9
8
7
6
5
i t a
n o
o c
m
m
a
d n
a
d n
a d
a t
M
1
C
M
0
D
7
D
6
D
5
—
4
3
2
1
D
O I
_
D
O I
C
1
C
0
D
O I
_
D
O I
C
1
C
0
L
o
w
B
y
e t
(
t i b
7
o t
) 0
O
u
p t
t u
I
p n
t u
O
u
p t
t u
I
p n
t u
4
3
2
1
D
4
D
3
D
2
D
1
D
Advantech Co., Ltd.
www.advantech.com
0
_
_
0
0
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