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APPENDIX D
Table D-15: Register for counter gate and clock control/status
B
a
e s
A
d
. d
5 1
4 1
W
0 2
R
W
2 2
R
W
4 2
R
W
6 2
R
C
1 n
0
0
1
1
PCI-1712/1712L User's Manual
3 1
2 1
1 1
0 1
9
C
o
n u
r e t
C
o
n u
r e t
G
A
- T
C
L
K
0
O
U
E
0 S
C
o
n u
r e t
C
o
n u
r e t
G
A
- T
C
L
K
1
O
U
E
1 S
C
o
n u
r e t
C
o
n u
r e t
G
A
- T
C
L
K
2
O
U
E
2 S
C
o
n u
r e t
n i
r e t
Table D-16 : Table of Cn1 to Cn0 register
C
0 n
0
1
0
1
[Cn1: Cn0] = [0, 0], write CQn to set the counter clock. Refer
to CQn description.
[Cn1: Cn0] = [0, 1], The internal clock is generated by an on-
board oscillator.
[Cn1: Cn0] = [1, 0], External clock is on connector
CNTn_CLK (n = 0, 1, 2).
[Cn1: Cn0] = [1, 1], The clock source of every counter
– 96 –
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8
7
6
5
0
a g
e t
a
d n
c
o l
k c
c
n o
r t
l o
G
R
0
G
Q
0
G
0 P
G
1 0
0
a g
e t
a
d n
c
o l
k c
s
t a t
s u
G
A
- T
T
0
G
Q
0
G
0 P
G
1 0
E
0
1
a g
e t
a
d n
c
o l
k c
c
n o
r t
l o
G
R
1
G
Q
1
G
1 P
G
1 1
1
a g
e t
a
d n
c
o l
k c
s
t a t
s u
G
A
- T
T
1
G
Q
1
G
1 P
G
1 1
E
1
2
a g
e t
a
d n
c
o l
k c
c
n o
r t
l o
G
R
2
G
Q
2
G
2 P
G
1 2
2
a g
e t
a
d n
c
o l
k c
s
t a t
s u
G
A
- T
T
2
G
Q
2
G
2 P
G
1 2
E
2
a n
c l
o l
k c
o s
r u
e c
s
l e
c e
r t
g e
s i
N
A /
C
o l
k c
C
o l
k c
o c
m
C
o l
k c
o c
m
C
o l
k c
o c
m
e
f s
—
4
3
2
1
G
0 0
C
Q
0
C
0 P
C
1 0
C
G
0 0
C
Q
0
C
0 P
C
1 0
C
G
0 1
C
Q
1
C
1 P
C
1 1
C
G
0 1
C
Q
1
C
1 P
C
1 1
C
0 1
G
0 2
C
Q
2
C
2 P
C
1 2
C
0 2
G
0 2
C
Q
2
C
2 P
C
1 2
C
0 2
r e t
C
L
K
- _
C
L
S
E
L
1
S
E
M
a e
i n
g n
s i
s
t e
y b
C
Q
n
e
f s
o r
m
n i
r e t
a n
c l
o l
k c
e
f s
o r
m
x e
r e t
a n
c l
o l
k c
o r
m
r p
v e
o i
s u
o c
n u
e t
s ' r
o
t u
Advantech Co., Ltd.
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0
0 0
0 0
0 1
K
- _
L
0
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