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APPENDIX D
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PCI-1712/1712L User's Manual
Table D-9: Register for interrupt and FIFO status
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This bit indicates whether interrupt occurred or not.
1 means that an interrupt has occurred.
This bit indicates the A/D FIFO empty status
1 means A/D FIFO empty.
This bit indicates the A/D FIFO half-full status
1 means A/D FIFO halt-full.
This bit indicates the A/D FIFO full status
1 means A/D FIFO full.
This bit indicates the D/A FIFO empty status
1 means D/A FIFO empty.
This bit indicates the D/A FIFO half-full status
1 means D/A FIFO halt-full.
This bit indicates the D/A FIFO full status
1 means D/A FIFO full.
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