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This bit is read only which indicates the status of the pulse
width measurement state machine. "1" means the measure
ment is in process; "0" means the measurement is complete.
This clock is for counter 0 to 2 internal clock source.
The register sets the frequency of internal clock source of
counter 0 to counter 2.
Table D-18: Table for CLK_SEL1 to CLK_SEL0 register
C
L
K
S _
E
L
1
C
L
0
0
1
1
B
a
e s
A
d
. d
5 1
4 1
W
D
O
5 1
D
O
4 1
D
8 2
R
D
O
5 1
D
O
4 1
D
The PCI-1712/1712L provides 16 digital I/O channels. Each group of 8
channels can be defined as both input or output channels. You can
configure digital input/output by setting the digital I/O configuration
register. Refer to next section for more details.
DO0 is the least significant bit (LSB) of the digital output
data.
DO15 is the most significant bit (MSB) of the digital output
data.
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K
S _
E
L
0
0
1
0
1
Table D-19: Register for Digital I/O
3 1
2 1
1 1
0 1
9
O
3 1
D
O
2 1
D
O
1 1
D
O
0 1
D
O
9
O
3 1
D
O
2 1
D
O
1 1
D
O
0 1
D
O
9
M
a e
i n
g n
n I
r e t
a n
c l
o l
k c
s i
0 1
n I
r e t
a n
c l
o l
k c
s i
1
n I
r e t
a n
c l
o l
k c
s i
1
0 0
n I
r e t
a n
c l
o l
k c
s i
0 1
8
7
6
5
D
i g i
l a t
O
u
p t
t u
D
O
8
D
O
7
D
O
6
D
O
5
D
D
g i
a t i
I l
p n
t u
D
O
8
D
O
7
D
O
6
D
O
5
D
– 99 –
PCI-1712/1712L User's Manual
APPENDIX D
M
H
z
M
H
z
K
H
z
K
H
z
4
3
2
1
0
O
4
D
O
3
D
O
2
D
O
1
D
O
0
O
4
D
O
3
D
O
2
D
O
1
D
O
0
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