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APPENDIX D
B
a
e s
A
d
. d
5 1
0 3
W
Note
This base addresse is used for continuous output operation mode only.
If the two D/A channels are both operating in continuous output mode,
the data in FIFO will be sent in an interlaced manner, i.e. The "even"
samples in the FIFO are sent to D/A channel 0, while the "odd" samples
to D/A channel 1.
PCI-1712/1712L User's Manual
—
Table D-24: Register for D/A channel data
4 1
3 1
2 1
1 1
0 1
D
A /
c
a h
n n
l e
a d
D
A
1 1
D
A
0 1
DA0 is the least significant bit (LSB) of the D/A data
DA11 is the most significant bit (MSB).
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9
8
7
6
a t
f
r o
c
n o
n i t
o u
s u
u o
p t
t u
p o
D
A
9
D
A
8
D
A
7
D
A
6
D
– 102 –
5
4
3
2
1
r e
i t a
n o
m
o
e d
A
5
D
A
4
D
A
3
D
A
2
D
A
1
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0
D
A
0
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