Single Channel Ddr Signal Termination And Decoupling; Decoupling Requirements; Single Channel Ddrcvo Single Channel Routing Guidelines - Intel Xeon Design Manual

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Intel Xeon™ Processor and Intel
Table 22. DDRCVO Routing Guidelines
Topology
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH to Divider
Figure 24. Single Channel DDRCVO Single Channel Routing Guidelines
3.3.8

Single Channel DDR Signal Termination and Decoupling

Follow design guidelines provided in the Intel
Chipset Compatible Platform Design Guide.
3.3.9 2.5 V Decoupling Requirements
Decouple the DIMM connectors as shown in
(0603) capacitors between each pair of DIMM connectors. Place two Tantalum 100 µF capacitors
around each DIMM connector and two additional Tantalum 100 µF capacitors per channel, keeping
them within 0.5 inch of the DIMM connectors.
decoupling scheme and
42
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E7500/E7501 Chipset Compatible Platform
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Parameter Intel
MCH
Figure 26 depicts a single channel 4-DIMM decoupling scheme.
E7501 Chipset MCH
Resistor Divider
15 mils
20 mils
< 1.0"
DDR VDD
(2.5V)
49.9 Ω Ω Ω Ω ± 1%
< 1"
DDRCVO_A
49.9 Ω ± 1% Ω ± 1% Ω ± 1% Ω ± 1%
®
Xeon™ Processor and Intel
Figure 25 or Figure
Figure 25 depicts a single Channel 2-DIMM
Platform Design Guide Addendum
1 nF
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E7500/E7501
26. Place six ceramic 0.1 µF