Intel Pentium III Processor 512K Design Manual page 5

Tables
1 Related Documents ...................................................................................................................... 7
2 Micro-FCBGA Package Mechanical Specifications ....................................................................11
3 System Timing Equations ...........................................................................................................13
4 System Timing Terms.................................................................................................................13
5 System Bus Timing Parameters .................................................................................................14
6 Sample CPU to CPU flight time calculations ..............................................................................14
7 Trace Lengths for "T" Topology (ServerWorks Chipset).............................................................15
8 Component Values for T Topology .............................................................................................15
9 Wired-OR Values........................................................................................................................16
10 System Signal Layout Guidelines ...............................................................................................20
11 JTAG Signal Layout Guidelines..................................................................................................20
12 Execution Signals Routing Guidelines........................................................................................21
13 Debug Port Termination Requirement ........................................................................................22
14 Routing Guidelines .....................................................................................................................23
15 Component Values for SE Clocking Topology............................................................................26
16 CLKREF Component Values ......................................................................................................27
17 BSEL[1:0] Encoding....................................................................................................................28
18 LV Intel Pentium
19 THERMTRIP# Timing Requirements..........................................................................................38
20 AGTL Signals..............................................................................................................................40
21 CMOS Signals ............................................................................................................................41
22 TAP/ITP Signals .........................................................................................................................42
23 Clock Signals ..............................................................................................................................42
24 Miscellaneous Signals ................................................................................................................43
25 Power Signals.............................................................................................................................44
Design Guide
®
LV Intel Pentium
processor 512K Bulk Capacitance Recommendations ...............................35
III
®
III Processor 512K Dual Processor Platform
5