Jtag Signals Tdi/Tdo For Processor Only; Routing Guidelines - Intel Pentium III Processor 512K Design Manual

3.9.1.3

Routing Guidelines

Table 14. Routing Guidelines
Parameter
TCK
TMS, TDO, TDI,
POWERON,
DBRESET#,
BSEN#,
DBINST#,
PREQx#
TRST#
PRDYx#
RESET#
3.9.1.4 System Implementation
Figure 10 demonstrates the expected route of the JTAG data link for a processor only cluster. It is
obligatory to pull up TDI/TDO for each signal.
Figure 10. JTAG Signals TDI/TDO for Processor Only
Design Guide
®
LV Intel Pentium
Reference Figure
1" max from debug port to RT AND 12" max from debug port to
Figure 7
processor VERY SENSITIVE TO NOISE -- please route accordingly
1" max from debug port to RT AND 12" max from debug port to
Figure 6 (a)
processor
1" max from debug port to RT AND 12" max from debug port to
Figure 6 (b)
processor
1" max from debug port to RS AND 1" max from debug port to RT
Figure 8
AND 12" max from debug port to processor (AGTL guidelines)
1" max from debug port to RS AND 1" max from debug port to RT
Figure 9
AND 12" max from debug port to processor
VCC_CMOS
CPU0
TDI
TDO
®
III Processor 512K Dual Processor Platform
Description
CPU1
TDO TDI
VCC_CMOS
VCC_CMOS
ITP Port
23