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Low-Power Module Memory Bus Simulation Methodology
2.0
Simulation Prerequisites
The following information is needed to simulate the Low-Power Module memory bus:
•
Pentium
(contact your Intel Field Sales Representative)
— Module interconnect specifications
— Connector parameters
•
82443BX Electrical and Thermal Timing Specifications datasheet addendum, Rev 1.0
(order number: 273218)
— 82443BX AC and DC Specifications
•
4-Clock 66 MHz 72-Bit ECC Unbuffered SDRAM DIMM Design Specification, Rev 1.0
(http://developer.intel.com/)
— DIMM board layout
— SDRAM AC and DC specifications
•
I/O Buffer Models
— 82443BX IBIS model, Rev 1.2 (contact your Intel Field Sales Representative). The
82443BX IBIS model is used for the Intel
— SDRAM component IBIS models. The 66-MHz unbuffered SDRAM IBIS models are
available in x8 and x16 configurations from various memory manufacturers.
3.0
Simulation Block Diagram
Figure 1 shows the simulation block diagram for the Low-Power Module/DIMM memory
interface. The Pentium II Processor Mobile Module MMC-2 I/O Buffer Model describes the
interconnect characteristics between the Low-Power Module 400-pin connector, and the 82443BX
Host Bridge/Controller.
As shown in Figure 1, the 400-pin connector is used to model the net (TL-1) and the 400-pin
connector model. The 4-clock, 66-MHz, 72-bit Unbuffered SDRAM DIMM specification, which
describes the interconnect characteristics of the SDRAM DIMM, is used to model the nets (TL-3,
TL-4, TL-5, TL-6) of DIMM. Based on all the corners of simulations, as described in Section 5.0,
the interconnect on the system electronics (SE) board (TL-2) can be specified to meet the setup/
hold requirements for both the SDRAM and 82443BX Host Bridge/Controller.
6
®
II Processor Mobile Module MMC-2 I/O Buffer Model Specification, Rev 1.0
®
440BX AGPset chipset.
Application Note
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