Hardware Overview - AMD XILINX T2 User Manual

CB processing with HARQ buffer management in lookaside mode
○
Note: The Zynq UltraScale+ RFSoC ZU48DR device also supports concurrent 4G LTE/5G NR L1 offload,
assuming that the necessary hardware resources are available.
The T2 card value proposition is in offloading CPU intensive encode and decode computations
involving LDPC operations, thereby reducing costly CPU resources. The Zynq UltraScale+ RFSoC
has hard IP blocks for SD-FEC (eight SD-FEC cores per device) which can be configured to run
LDPC encode and decode operations.

Hardware Overview

The following high-level block diagram of the T2 card provides an overview of the hardware
features.
HHHL Single Slot
OSC
50 MHz
OSC
300 MHz
SC MSP432
The T2 card hardware features are as follows:
• Zynq UltraScale+ RFSoC device targeting L1 channel coding
• NOR flash (2x 256 MB in dual QSPI mode) for ZU48DR Zynq UltraScale+ RFSoC image
storage
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
Figure 2: T2 Card High-Level Block Diagram
NOR
XCZU48DR- 2FSVG1517E
Flash
Zynq UltraScale+ RFSoC
X8
1GB
DDR4
x16
PS DDR
Controller
1GB
DDR4
(Bank 504)
x16
ECC x8
(Bank 128, 129, 130, 131)
PCIe Gen3 x16 /
PCIe Gen4 x8 Bifurcated
12V 3.3V
PS MIO
PL DDR
(Bank
Controller
500)
(Bank 67,
8x SD-FEC
68, 69)
(LDPC/Turbo)
PL GTY PCIe 4
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Chapter 1: Introduction
1GB
DDR4
x16
1GB
DDR4
x16
Power
1GB
Supply
DDR4
Unit
x16
1GB
DDR4
x16
ECC x8
X25345-051221
www.xilinx.com
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