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Vega 10
AMD Vega 10 Manuals
Manuals and User Guides for AMD Vega 10. We have
1
AMD Vega 10 manual available for free PDF download: Data Book
AMD Vega 10 Data Book (188 pages)
Brand:
AMD
| Category:
Video Card
| Size: 1.95 MB
Table of Contents
Table of Contents
5
Chapter 1 Introduction
13
Part Identification
13
Packaging Types and Device Ids
13
Table 1-1 Package Information
13
Branding Format
14
Figure 1-1 "Vega 10" Branding
14
Chapter 2 Functional Overview
15
Memory Interface
15
Memory Configurations Support
15
Memory Aperture Size
16
Table 2-1 HBM Configurations
16
Acceleration Features
17
Display System
18
Display Features
19
Figure 2-1 "Vega 10" Display Top-Level Data-Flow Diagram
19
DVI/Hdmi™/Displayport/Embedded Displayport Features
20
DVI/HDMI™ Features
20
Table 2-2 HDMI Features
21
Displayport (DP) and Embedded Displayport (Edp) Features
22
Table 2-3 Maximum Pixel Rates for 4, 2, or 1 Lane(S) at 8.1-Ghz Link Rate
23
Integrated HD-Audio Controller (Azalia) and Codec
24
Video Acceleration Features
25
Video Codec Engine (VCE) Features
26
PCI Express® Bus Support Features
27
Power Management Features
27
Spread-Spectrum Support
28
Engine Spread-Spectrum Support
28
Displayport Internal Spread-Spectrum Support
28
Internal Thermal Sensor
28
Thermal Diode
28
Logo Compliance
29
Test Capability Features
29
Other Features
29
Export Control Classification
30
Chapter 3 Signal Descriptions
31
Pin Assignments
32
Chapter 3 Signal Descriptions
32
Table 3-1 Pin Assignments (Left Half)
32
PCI Express® Bus Interface
33
Table 3-2 Pin Assignments (Right Half)
33
Memory Interface (HBM)
34
Table 3-3 PCI Express Bus Interface
34
Table 3-4 Memory Interface
34
Display Configuration Overview
35
Integrated HDMI™/TMDS Interface
35
2017 Advanced Micro Devices, Inc
35
Table 3-5 Display Configuration Overview for Links A, B, C, D, E, and F
35
Displayport
36
Table 3-6 Integrated HDMI/TMDS Interface
36
Table 3-7 Displayport Interface
37
Hardware I2 C Interface
38
Serial Flash Interface
38
Table 3-8 Hardware IC Interface
38
Table 3-9 Serial Flash Interface
38
General Purpose I/O Interface
39
Table 3-10 General Purpose I/O Interface
39
AMD SVI2 Master Interface
41
Panel Control Interface
41
Table 3-11 AMD SVI2 Master Interface
41
Table 3-12 Panel Control Interface
41
Global Swap Lock on Multiple Gpus
42
Table 3-13 Global Swap Lock on Multiple Gpus
42
Display Identification Interface
43
Table 3-14 Display Identification Interface
43
Test/Jtag Interface
44
Table 3-15 Test/Jtag Interface
44
Debug Port
45
Thermal Information and Management Interface
45
Table 3-16 Debug Port
45
Table 3-17 Thermal Interface Signals
45
Smbus Interface
46
Table 3-18 Smbus Interface
46
PLL Interface
47
Table 3-19 PLL Interface
47
Table 3-20 External Input Clock Requirements for REFCLKN/P
47
AMD Powerxpress Interface
48
Power and Ground Descriptions and Operating Conditions
48
Table 3-21 AMD Powerxpress Interface
48
Table 3-22 Power and Ground Descriptions and Operating Conditions
48
Configuration Straps
49
Pin-Based Straps
49
Table 3-23 Other Signals
49
Table 3-24 Pin-Based Straps
50
ROM Configurations
52
ROM Straps for Add-In Card Design
52
Table 3-25 Rom-Based Straps
53
Chapter 4 Timing Specifications
55
Smbus Timing
55
Smbus Write Cycle
55
Figure 4-1 Smbus Write Cycle
55
Smbus Read Cycle
57
Figure 4-2 Smbus Read Cycle
57
Smbus Read Thermal Sensor
58
Initialization Sequence and Timing
59
Standard Boot-Up Sequence
60
Figure 4-3 Reset Sequence
60
Table 4-1 Power-On Reset Sequence Timing Parameters
60
Serial Flash Read/Write Timing
62
Chapter 4 Timing Specifications
62
Figure 4-4 Serial Flash Write/Read Timing
62
Table 4-2 Serial Flash Write/Read Timing Parameters for the Bootup Case
62
LCD Panel Power-Up/Down Timing (Edp Interface)
63
Figure 4-5 Edp Panel Power-Up/Down Timing
63
Table 4-3 Registers for Setting Backlight PWM Parameters
63
LCD Panel Backlight Control with PWM
64
Figure 4-6 Backlight PWM Parameters
64
Table 4-4 Registers for Setting Backlight PWM Parameters
65
Table 4-5 Backlight PWM Parameters
67
Chapter 5 Electrical Characteristics
69
Maximum Voltage
69
Table 5-1 Maximum Voltage
69
Electrical Design Power
70
Table 5-2 Regulator Guidelines
70
Transient Behavior
71
Figure 5-1 Load Insertion Legend
72
Figure 5-2 Load Release Legend
72
Table 5-3 Load Insertion Behavior
72
Table 5-4 Load Release Behavior
72
Power-Up/Down Sequence
73
TTL Interface Electrical Characteristics
73
DDC I2C Mode Electrical Characteristics
73
Table 5-5 DC Characteristics for 3.3-V GPIO Pads
73
Displayport AUX Electrical Specification
74
Chapter 5 Electrical Characteristics
74
Table 5-6 Transmitter Electrical Specification for DDC I2C
74
Table 5-7 Receiver Electrical Specification for DDC I2C Pins
74
Table 5-8 Displayport AUX Electrical Specification
74
Displayport Main Link Electrical Characteristics
75
Smbus Electrical Characteristics
75
Table 5-9 Displayport Main Link Electrical Specification
75
Table 5-10 Transmitter Electrical Specification
75
Table 5-11 Receiver Electrical Specification
75
Chapter 6 Thermal Data
77
Thermal Models
77
Thermal Characteristics
77
Table 6-1 ASIC Compact Thermal Model
77
Table 6-2 Thermal Characteristics
77
Thermal Design Power
78
Thermal Diode Characteristics
78
Table 6-3 TGP for Discrete Variants
78
Storage Requirements
79
Chapter 7 Mechanical Data
81
Physical Dimensions
81
Vega 10" Physical Dimensions
81
Figure 7-1 "Vega 10" Package Outline (Preliminary-MOD-00370 REV 01)
82
Figure 7-2 "Vega 10" Package Outline (Preliminary-MOD-00370 REV 01) Top View
83
Figure 7-3 "Vega 10" Ball Names (Bottom View)
84
Pressure Specification
85
Board Solder Reflow Process Recommendations
85
Stencil Opening Size for Solderball Pads on PCB
85
FCBGA Reference Reflow Profile for Rohs/Lead-Free Solder
86
Figure 7-4 FCBGA Reference Reflow Profile for Rohs/Lead-Free SMT
86
Table 7-1 Recommended Profiling - Rohs/Lead-Free Solder
87
Chapter 8 Boundary Scan Specification
89
Introduction
89
Boundary Scan
89
JTAG Interface Signals
89
Chapter 1 Introduction
89
Table 8-1 JTAG Interface
89
JTAG Timing Characteristics
90
Figure 8-1 Timing of the Boundary Scan Signals with Respect to TCK
90
Figure 8-2 Timing of the TAP Ports (TDI, TMS, and TDO) with Respect to TCK
90
Table 8-2 JTAG Timing Characteristics
90
Appendix A Pin Listings
91
Pins Sorted by Ball Reference
91
Table A-1 Pins Sorted by Ball Reference
91
Pins Sorted by Signal Name
139
Table A-2 Pins Sorted by Signal Name
139
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