Ddr4 Ps Interface - AMD XILINX T2 User Manual

Table 2: DDR4 PL Interface Pin Map (cont'd)
Pin Number
H20
K21
K22
D23
D24
K12
K10
E11
F12
K11
H8
G8
K13
F11
D14
J10
J14
J13

DDR4 PS Interface

The DDR4 PS interface is 40 bit (32 bits with 8-bit ECC) and operates at a maximum rate of
DDR2400.
Using the DDR4 PS Interface
• The DDR4 PS interface is supported with a dedicated IP block that must be enabled in the
design.
• The memory devices on the board are Micron MT40A512M16LY-062E:E (8 Gb 512Mx16).
• The maximum rate of DDR2400 is a Zynq
DDR4 PS Interface Pins
The following table summarizes the ZU48DR DDR4 PS interface pin map.
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
Signal Name
PL_DDR4_1_DQS6#
PL_DDR4_1_DQS7
PL_DDR4_1_DQS7#
PL_DDR4_1_DQS8
PL_DDR4_1_DQS8#
PL_DDR4_1_ODT
PL_DDR4_1_PAR
PL_DDR4_1_RAS#
PL_DDR4_1_CAS#
PL_DDR4_1_ACT#
PL_DDR4_1_CK
PL_DDR4_1_CK#
PL_DDR4_1_CKE
PL_DDR4_1_CS#
PL_DDR4_1_WE#
PL_DDR4_1_ALERT#
PL_DDR4_1_RST#
PL_DDR4_1_TEN
Description
DDR4 Data Strobe 6 (N)
DDR4 Data Strobe 7 (P)
DDR4 Data Strobe 7 (N)
DDR4 Data Strobe 8 (P)
DDR4 Data Strobe 8 (N)
DDR4 On Die Termination
DDR4 Parity
DDR4 Row Address Strobe
DDR4 Column Address Strobe
DDR4 Activate
DDR4 Clock (P)
DDR4 Clock (N)
DDR4 Clock Enable
DDR4 Chip Select
DDR4 Write Enable
DDR4 Alert
DDR4 Reset
DDR4 Test Enable
® UltraScale+™ RFSoC -2E device limitation.
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Chapter 3: Pin Mapping
I/O
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
O
O
O
O
O
O
O
O
O
O
I
O
O
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