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26
3.7 Hardware I
Table 3–8 Hardware IC Interface
Pin
Name
SCL
SDA
3.8 Serial Flash Interface
Configuration straps must be set to identify the appropriate ROM type. See
Configuration Straps (p.
Table 3–9 Serial Flash Interface
Pin Name
GPIO_9_ROMSO
GPIO_8_ROMSI
GPIO_7_ROMSCK
GPIO_10_ROMCSB
"Vega 10" Databook
56006_1.00
2
C Interface
I/O
Description
I
2
C clock.
I/O
Note: Can be left unconnected if not used.
(VDDAN_33)
Frequency: Up to 100 KHz I
fast mode plus.
I
2
C clock.
I/O
Note: Can be left unconnected if not used.
(VDDAN_33)
Frequency: Up to 100 KHz I
fast mode plus.
37).
Type
I
PD-reset
(VDDAN_33)
O
PD-reset
(VDDAN_33)
O
PD-reset
(VDDAN_33)
O
PU-reset
(VDDAN_33)
2
C standard; Up to 400 KHz fast; and up to 1 MHz
2
C standard; Up to 400 KHz fast; and up to 1 MHz
PD/PU
Serial-ROM output from ROM.
General purpose I/O or open-drain output.
Serial-ROM input to ROM.
General purpose I/O or open-drain output.
Serial-ROM clock to ROM.
General purpose I/O or open-drain output.
BIOS-ROM chip select.
Used to enable the ROM for ROM read and program
operations.
Signal Descriptions
Description
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
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