AMD XILINX T2 User Manual page 12

DDR4 PL Interface Pins
The following table summarizes the ZU48DR DDR4 PL interface pin map.
Table 2: DDR4 PL Interface Pin Map
Pin Number
G12
G13
G9
G6
J8
H7
F9
K9
G7
J7
J9
H6
E13
H12
E12
G14
E14
H13
F14
C12
N14
J15
G17
C23
D18
J23
N20
F21
A14
A11
B14
C13
B13
D13
A15
UG1496 (v1.0) June 15, 2022
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Signal Name
RF_CLK_DDR_N
RF_CLK_DDR_P
PL_DDR4_1_A0
PL_DDR4_1_A1
PL_DDR4_1_A2
PL_DDR4_1_A3
PL_DDR4_1_A4
PL_DDR4_1_A5
PL_DDR4_1_A6
PL_DDR4_1_A7
PL_DDR4_1_A8
PL_DDR4_1_A9
PL_DDR4_1_A10
PL_DDR4_1_A11
PL_DDR4_1_A12
PL_DDR4_1_A13
PL_DDR4_1_BA0
PL_DDR4_1_BA1
PL_DDR4_1_BG0
PL_DDR4_1_DM0#
PL_DDR4_1_DM1#
PL_DDR4_1_DM2#
PL_DDR4_1_DM3#
PL_DDR4_1_DM4#
PL_DDR4_1_DM5#
PL_DDR4_1_DM6#
PL_DDR4_1_DM7#
PL_DDR4_1_DM8#
PL_DDR4_1_DQ0
PL_DDR4_1_DQ1
PL_DDR4_1_DQ2
PL_DDR4_1_DQ3
PL_DDR4_1_DQ4
PL_DDR4_1_DQ5
PL_DDR4_1_DQ6
Description
DDR4 Diff Clock Input (N)
DDR4 Diff Clock Input (P)
DDR4 Address 0
DDR4 Address 1
DDR4 Address 2
DDR4 Address 3
DDR4 Address 4
DDR4 Address 5
DDR4 Address 6
DDR4 Address 7
DDR4 Address 8
DDR4 Address 9
DDR4 Address 10
DDR4 Address 11
DDR4 Address 12
DDR4 Address 13
DDR4 Bank Address 0
DDR4 Bank Address 1
DDR4 Bank Group 0
DDR4 Data Mask 0
DDR4 Data Mask 1
DDR4 Data Mask 2
DDR4 Data Mask 3
DDR4 Data Mask 4
DDR4 Data Mask 5
DDR4 Data Mask 6
DDR4 Data Mask 7
DDR4 Data Mask 8
DDR4 Data I/O 0
DDR4 Data I/O 1
DDR4 Data I/O 2
DDR4 Data I/O 3
DDR4 Data I/O 4
DDR4 Data I/O 5
DDR4 Data I/O 6
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Chapter 3: Pin Mapping
I/O
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
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