AMD XILINX T2 User Manual page 16

Table 3: DDR4 PS Interface Pin Map
Pin Number
AV31
AW28
AV28
AU29
AW31
AU28
AL29
AM30
AM29
AP29
AT31
AT32
AT30
AU32
AN30
AM32
AN32
AU23
AT27
AL24
AM27
AR38
AV22
AW24
AW23
AV25
AR23
AW25
AV23
AR24
AP26
AV27
AT25
AW26
AR27
AU27
AU25
AV26
AK24
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
Signal Name
PS_DDR4_1_A0
PS_DDR4_1_A1
PS_DDR4_1_A2
PS_DDR4_1_A3
PS_DDR4_1_A4
PS_DDR4_1_A5
PS_DDR4_1_A6
PS_DDR4_1_A7
PS_DDR4_1_A8
PS_DDR4_1_A9
PS_DDR4_1_A10
PS_DDR4_1_A11
PS_DDR4_1_A12
PS_DDR4_1_A13
PS_DDR4_1_BA0
PS_DDR4_1_BA1
PS_DDR4_1_BG0
PS_DDR4_1_DM0#
PS_DDR4_1_DM1#
PS_DDR4_1_DM2#
PS_DDR4_1_DM3#
PS_DDR4_1_DM4#
PS_DDR4_1_DQ0
PS_DDR4_1_DQ1
PS_DDR4_1_DQ2
PS_DDR4_1_DQ3
PS_DDR4_1_DQ4
PS_DDR4_1_DQ5
PS_DDR4_1_DQ6
PS_DDR4_1_DQ7
PS_DDR4_1_DQ8
PS_DDR4_1_DQ9
PS_DDR4_1_DQ10
PS_DDR4_1_DQ11
PS_DDR4_1_DQ12
PS_DDR4_1_DQ13
PS_DDR4_1_DQ14
PS_DDR4_1_DQ15
PS_DDR4_1_DQ16
Description
DDR4 Address 0
DDR4 Address 1
DDR4 Address 2
DDR4 Address 3
DDR4 Address 4
DDR4 Address 5
DDR4 Address 6
DDR4 Address 7
DDR4 Address 8
DDR4 Address 9
DDR4 Address 10
DDR4 Address 11
DDR4 Address 12
DDR4 Address 13
DDR4 Bank Address 0
DDR4 Bank Address 1
DDR4 Bank Group 0
DDR4 Data Mask 0
DDR4 Data Mask 1
DDR4 Data Mask 2
DDR4 Data Mask 3
DDR4 Data Mask 4
DDR4 Data I/O 0
DDR4 Data I/O 1
DDR4 Data I/O 2
DDR4 Data I/O 3
DDR4 Data I/O 4
DDR4 Data I/O 5
DDR4 Data I/O 6
DDR4 Data I/O 7
DDR4 Data I/O 8
DDR4 Data I/O 9
DDR4 Data I/O 10
DDR4 Data I/O 11
DDR4 Data I/O 12
DDR4 Data I/O 13
DDR4 Data I/O 14
DDR4 Data I/O 15
DDR4 Data I/O 16
Send Feedback
Chapter 3: Pin Mapping
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
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