Chapter 3: Pin Mapping; Pcie Interface - AMD XILINX T2 User Manual

Pin Mapping
This chapter presents the pin mapping for the ZU48DR Zynq
card.

PCIe Interface

The PCIe ® interface on the T2 card has 16 lanes and can operate in Gen 3 x16 mode or Gen 4
x8x8 bifurcated mode.
Using the PCIe Interface
• The PCIe interface is supported with a dedicated IP block that must be instantiated in the
design.
• PCIe lane reversal is in use.
• The server slot used with the T2 card must be a x16 capable and configured correctly for card
detection and use. The Gen 4 x8x8 mode of operation requires x8 bifurcation to be enabled,
whereas Gen 3 x16 requires x16 mode.
PCIe Interface Pins
The following table summarizes the ZU48DR PCIe interface pin map.
Table 1: PCIe Interface Pin Map
Pin Number
W34
W33
P32
P31
AJ13
AA39
AA38
W39
W38
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
Signal Name
PCIE_RF_LOWER_REFCLK_N
PCIE_RF_LOWER_REFCLK_P
PCIE_RF_UPPER_REFCLK_N
PCIE_RF_UPPER_REFCLK_P
PCIE_RF_PERST_LS
PCIE_RX0_N
PCIE_RX0_P
PCIE_RX1_N
PCIE_RX1_P
® UltraScale+™ RFSoC on the T2
Description
PCIe Lower Diff Clock (N)
PCIe Lower Diff Clock (P)
PCIe Upper Diff Clock (N)
PCIe Upper Diff Clock (P)
PCIe Reset
PCIe RX Data 0 (N)
PCIe RX Data 0 (P)
PCIe RX Data 1 (N)
PCIe RX Data 1 (P)
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Chapter 3: Pin Mapping

Chapter 3
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