AMD XILINX T2 User Manual
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AMD XILINX T2 User Manual

AMD XILINX T2 User Manual

Telco accelerator card
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T2 Telco Accelerator Card
User Guide
UG1496 (v1.0) June 15, 2022
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  • Page 1 T2 Telco Accelerator Card User Guide UG1496 (v1.0) June 15, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs.

  • Page 2: Table Of Contents

    Table of Contents Chapter 1: Introduction ....................3 Hardware Overview........................4 Software Overview........................5 Zynq UltraScale+ RFSoC Specification..................5 Chapter 2: Features ....................... 7 Chapter 3: Pin Mapping ....................9 PCIe Interface..........................9 DDR4 PL Interface........................11 DDR4 PS Interface........................15 Special Functions........................18 Chapter 4: Maintenance Port .................21 Chapter 5: Power...

  • Page 3: Chapter 1: Introduction

    Chapter 1: Introduction Chapter 1 Introduction The Xilinx ® T2 Telco accelerator card, shown in the following figure, is a single slot, half height, half length (HHHL) plug-in card. It is compliant with PCI Express ® technology, supporting PCIe Gen3 x16 and Gen4 x8 bifurcated rates on the host interface. Figure 1: T2 Telco Accelerator Card ®...

  • Page 4: Hardware Overview

    Chapter 1: Introduction CB processing with HARQ buffer management in lookaside mode ○ Note: The Zynq UltraScale+ RFSoC ZU48DR device also supports concurrent 4G LTE/5G NR L1 offload, assuming that the necessary hardware resources are available. The T2 card value proposition is in offloading CPU intensive encode and decode computations involving LDPC operations, thereby reducing costly CPU resources.

  • Page 5: Software Overview

    Chapter 1: Introduction • 4 GB of DDR4 programmable logic (PL) memory • 2 GB of DDR4 processor system (PS) memory • MSP432-based satellite controller (SC) for card monitoring and telemetry • PCIe Gen 3 x16 or Gen 4 x8 bifurcated host interface •...
  • Page 6 Chapter 1: Introduction Figure 3: Zynq ® UltraScale+™ RFSoC XCZU48DR Device UG1496 (v1.0) June 15, 2022 www.xilinx.com Send Feedback T2 Telco Accelerator Card User Guide...

  • Page 7: Chapter 2: Features

    Chapter 2: Features Chapter 2 Features The main features of the T2 card are as follows: • Card over-stress protection: The T2 card has a card protection circuit that initiates a fatal shutdown if either temperature or power consumption thresholds are crossed. Before this threshold is reached, however, the SC signals to the Zynq UltraScale+ RFSoC to reduce the 5G workload power immediately.
  • Page 8 Chapter 2: Features • Developer support: Developer support features for the Zynq UltraScale+ RFSoC on the T2 card are provided through the maintenance port. See Chapter 4: Maintenance Port for details. • LED: A green power-on LED is present on the I/O bracket to indicate the card is powered and in operation.

  • Page 9: Chapter 3: Pin Mapping

    Chapter 3: Pin Mapping Chapter 3 Pin Mapping This chapter presents the pin mapping for the ZU48DR Zynq ® UltraScale+™ RFSoC on the T2 card. PCIe Interface The PCIe ® interface on the T2 card has 16 lanes and can operate in Gen 3 x16 mode or Gen 4 x8x8 bifurcated mode.
  • Page 10 Chapter 3: Pin Mapping Table 1: PCIe Interface Pin Map (cont'd) Pin Number Signal Name Description PCIE_RX2_N PCIe RX Data 2 (N) PCIE_RX2_P PCIe RX Data 2 (P) PCIE_RX3_N PCIe RX Data 3 (N) PCIE_RX3_P PCIe RX Data 3 (P) PCIE_RX4_N PCIe RX Data 4 (N) PCIE_RX4_P...

  • Page 11: Ddr4 Pl Interface

    Chapter 3: Pin Mapping Table 1: PCIe Interface Pin Map (cont'd) Pin Number Signal Name Description PCIE_TX5_P PCIe TX Data 5 (P) PCIE_TX6_N PCIe TX Data 6 (N) PCIE_TX6_P PCIe TX Data 6 (P) PCIE_TX7_N PCIe TX Data 7 (N) PCIE_TX7_P PCIe TX Data 7 (P) PCIE_TX8_N...
  • Page 12 Chapter 3: Pin Mapping DDR4 PL Interface Pins The following table summarizes the ZU48DR DDR4 PL interface pin map. Table 2: DDR4 PL Interface Pin Map Pin Number Signal Name Description RF_CLK_DDR_N DDR4 Diff Clock Input (N) RF_CLK_DDR_P DDR4 Diff Clock Input (P) PL_DDR4_1_A0 DDR4 Address 0 PL_DDR4_1_A1...
  • Page 13 Chapter 3: Pin Mapping Table 2: DDR4 PL Interface Pin Map (cont'd) Pin Number Signal Name Description PL_DDR4_1_DQ7 DDR4 Data I/O 7 Bidirectional PL_DDR4_1_DQ8 DDR4 Data I/O 8 Bidirectional PL_DDR4_1_DQ9 DDR4 Data I/O 9 Bidirectional PL_DDR4_1_DQ10 DDR4 Data I/O 10 Bidirectional PL_DDR4_1_DQ11 DDR4 Data I/O 11...
  • Page 14 Chapter 3: Pin Mapping Table 2: DDR4 PL Interface Pin Map (cont'd) Pin Number Signal Name Description PL_DDR4_1_DQ46 DDR4 Data I/O 46 Bidirectional PL_DDR4_1_DQ47 DDR4 Data I/O 47 Bidirectional PL_DDR4_1_DQ48 DDR4 Data I/O 48 Bidirectional PL_DDR4_1_DQ49 DDR4 Data I/O 49 Bidirectional PL_DDR4_1_DQ50 DDR4 Data I/O 50...

  • Page 15: Ddr4 Ps Interface

    Chapter 3: Pin Mapping Table 2: DDR4 PL Interface Pin Map (cont'd) Pin Number Signal Name Description PL_DDR4_1_DQS6# DDR4 Data Strobe 6 (N) Bidirectional PL_DDR4_1_DQS7 DDR4 Data Strobe 7 (P) Bidirectional PL_DDR4_1_DQS7# DDR4 Data Strobe 7 (N) Bidirectional PL_DDR4_1_DQS8 DDR4 Data Strobe 8 (P) Bidirectional PL_DDR4_1_DQS8# DDR4 Data Strobe 8 (N)
  • Page 16 Chapter 3: Pin Mapping Table 3: DDR4 PS Interface Pin Map Pin Number Signal Name Description AV31 PS_DDR4_1_A0 DDR4 Address 0 AW28 PS_DDR4_1_A1 DDR4 Address 1 AV28 PS_DDR4_1_A2 DDR4 Address 2 AU29 PS_DDR4_1_A3 DDR4 Address 3 AW31 PS_DDR4_1_A4 DDR4 Address 4 AU28 PS_DDR4_1_A5 DDR4 Address 5...
  • Page 17 Chapter 3: Pin Mapping Table 3: DDR4 PS Interface Pin Map (cont'd) Pin Number Signal Name Description AM25 PS_DDR4_1_DQ17 DDR4 Data I/O 17 Bidirectional AP24 PS_DDR4_1_DQ18 DDR4 Data I/O 18 Bidirectional AN23 PS_DDR4_1_DQ19 DDR4 Data I/O 19 Bidirectional AK23 PS_DDR4_1_DQ20 DDR4 Data I/O 20 Bidirectional AP23...

  • Page 18: Special Functions

    Chapter 3: Pin Mapping Table 3: DDR4 PS Interface Pin Map (cont'd) Pin Number Signal Name Description AV30 PS_DDR4_1_CK# DDR4 Clock (N) AW30 PS_DDR4_1_CKE DDR4 Clock Enable AW29 PS_DDR4_1_CS# DDR4 Chip Select AR28 PS_DDR4_1_WE# DDR4 Write Enable AL32 PS_DDR4_1_ALERT# DDR4 Alert AM33 PS_DDR4_1_RST# DDR4 Reset...
  • Page 19 Chapter 3: Pin Mapping • In-band SC firmware update: Allows the SC firmware to be updated using PCIe technology. The I2C interface is connected to MIO pins of the Zynq ® UltraScale+™ RFSoC PS, meaning that an integrated IP solution is available. The I2C interface must be operated in slave mode and cannot be a master because the SC is the master, and drives an SCL clock.
  • Page 20 Chapter 3: Pin Mapping Table 4: Special Function Pin Map Pin Number Signal Name Description RF_QSPI_LWR_CLK QSPI Lower Clock AA26 RF_QSPI_LWR_CS# QSPI Lower Chip Select RF_QSPI_LWR_DQ0 QSPI Lower Data 0 Bidirectional RF_QSPI_LWR_DQ1 QSPI Lower Data 1 Bidirectional RF_QSPI_LWR_DQ2 QSPI Lower Data 2 Bidirectional RF_QSPI_LWR_DQ3 QSPI Lower Data 3...

  • Page 21: Chapter 4: Maintenance Port

    Chapter 4: Maintenance Port Chapter 4 Maintenance Port The T2 card card has a DMB II connector located at the rear of the card, on the opposite side of the I/O bracket. It serves as a maintenance port for developer access to the following ports: •...

  • Page 22: Chapter 5: Power

    Chapter 5: Power Chapter 5 Power The power consumption of the Zynq ® UltraScale+™ RFSoC XCZU48DR-2FSVG1517E device must be limited to a 40A maximum current draw on the combined V and SD-FEC rails. This CCINT limitation is rooted in the 0.85V POL powering these rails. It is expected that he 5G workload running on the Zynq UltraScale+ RFSoC can be accommodated well within this power limit.

  • Page 23: Chapter 6: Xilinx Design Constraints (Xdc) File

    Chapter 6: Xilinx Design Constraints (XDC) File Chapter 6 Xilinx Design Constraints (XDC) File RTL users can reference the Vivado Design Suite User Guide: Using Constraints (UG903) for more information. The T2 card card XDC file is available for download from the T Series lounge. Contact your Xilinx representative for access.

  • Page 24: Appendix A: Regulatory Compliance Statements

    Appendix A: Regulatory Compliance Statements Appendix A Regulatory Compliance Statements FCC Class A Products The products referred to in this document are listed below: • TA-T2-P6G-PQ-EV • TA-T2-P6G-PQ-DV Note: These devices are for use with UL Listed Servers or I.T.E. Regulatory compliance statements are valid for the production version of this product;...

  • Page 25: Emc Compliance

    Appendix A: Regulatory Compliance Statements EMC Compliance Class A Products The following standards apply: • FCC Part 15 – Radiated & Conducted Emissions (USA) • CAN ICES-3(A)/NMB-3(A) – Radiated & Conducted Emissions (Canada) • CISPR 32 – Radiated & Conducted Emissions (International) •...

  • Page 26: Vcci Class A Statement

    Appendix A: Regulatory Compliance Statements 1. This device may not cause harmful interference. 2. This device must accept any interference received, including interference that may cause undesired operation. CAUTION! This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC rules.

  • Page 27: Appendix B: Additional Resources And Legal Notices

    Appendix B: Additional Resources and Legal Notices Appendix B Additional Resources and Legal Notices Xilinx Resources For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Documentation Navigator and Design Hubs Xilinx ® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information.

  • Page 28: References

    Appendix B: Additional Resources and Legal Notices References For the full power, electrical, mechanical, and thermal specifications of the T2 card, see the T2 Telco Accelerator Card Data Sheet (DS1000). These documents provide supplemental material useful with this guide: 1. T2 Telco Accelerator Card Installation Guide (UG1527) 2.
  • Page 29 Appendix B: Additional Resources and Legal Notices www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https:/...

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