Ic Block Diagram - Yamaha DPX-530 Service Manual

IC BLOCK DIAGRAM

PCB-MAIN(1/3)
IC250 NJM2233BM
+
GND Vout V NC
8 7 6 5
BUFFER
BIAS
1 2 3 4
Vin 1 CTL Vin 2 NC
CONTROL-OUTPUT
CTL OUTPUT
L Vin 1
Vin 2
H
IC2A0 TC90A92AFG
Sync Sep
Clamp
85
27M
CVBS/Y
10bit ADC
S/N Dtector
CCD alice
90
C
94
Cb
92
Cr
Digital I/F
IC550 NC7SB3157P6X
6
1
B1
S
2 5
GND
Vcc
3 4
B0 A
Function Table
Inpu t (S) Fun ct ion
L B
Connected to A
0
B
Connected to A
H
1
H: HIGH Logic Level
L: LO W Logic Level
IC2H0 TAR5S33
IC2J0 TAR5S25
IC2K0 TAR5S15
CONTROL
GND
NOISE
42M
HD/VD
X`tal
2
75 76 97
D/A
reference
Clock
x 8
Gene.
Timing
3D comb
27M 4M
-4fsc DRAM
ID1
27M
8bit ADC
10-26
IC580 SN74LV14APW
1A
2A
3A
4A
5A
6A
1 5 V
IN
2
3 4 V
OUT
Function Table
CONTROL V
OUT
H ON
L
OFF
H=HIGH Logic Level
L=LOW Logic Level
7
6
clock
Vertical enhance
3line
LTI
comb
contrast adjust
delay adjust
A C C
color decord
Motion
TINT adjust
Det.
Color adjust
IIC-BUS
32 31
SCL
SDA
1 2
1Y
3 4
2Y
5 6
3Y
9 8
4Y
11 10
5Y
13 12
6Y
FUNCTION TABLE
(each inverter)
INPUT OUTPUT
A Y
H L
L H
DPX-530
51-74
656/601
ITU-R656
encode Format
42-50
55