Emif_12 8-Bit Asynchronous Writes On 5509A Emif Not Supported; Divide-By-16 Modes, Asynchronous Access Followed By Sdram Access Will Not Supply A Ready Signal To Cpu - Texas Instruments TMS320VC5509A Manual

TMS320VC5509A Silicon Errata
Advisory EMIF_12
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
Advisory EMIF_13
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
1.0 and 1.1
8-bit asynchronous writes are not supported; however, 8-bit asynchronous reads are
supported.
None
After Changing CE Control Registers and Disabling SDRAM Clock in Divide-by-8 and
Divide-by-16 Modes, Asynchronous Access Followed by SDRAM Access Will Not Supply
1.0 and 1.1
If the SDRAM clock (EMIF.CLKMEM) is set to divide-by-8 and divide-by-16 of the CPU clock
and if the user disables the SDRAM clock before accessing asynchronous memory, the EMIF
will fail to supply the ready signal to the CPU under the following two conditions:
•
Case 1:
SDRAM access
Switch off the SDRAM clock
Change CE Space Control Register to Asynchronous Mode
Perform an asynchronous access to the same CE space
•
Case 2:
SDRAM access
Switch off the SDRAM clock
Change CE Space Control Register to Asynchronous Mode
Perform an asynchronous access to a different CE space
This failure of the ready signal will make the CPU wait indefinitely.
Switch the SDRAM clock to divide-by-1 before programming the CE Space Control Register to
asynchronous memory.
8-Bit Asynchronous Writes on 5509A EMIF Not Supported
SPRZ200E
a Ready Signal to CPU
16