Transmit Interrupt Mask Set Register (Txintmaskset); Transmit Interrupt Mask Set Register (Txintmaskset) Field Descriptions - Texas Instruments TMS320C674X User Manual

EMAC Module Registers
5.9

Transmit Interrupt Mask Set Register (TXINTMASKSET)

The transmit interrupt mask set register (TXINTMASKSET) is shown in
Table 46.
Figure 47. Transmit Interrupt Mask Set Register (TXINTMASKSET)
31
15
7 6
TX7MASK TX6MASK
R/W1S-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset
Table 46. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
Bit Field Value
31-8 Reserved 0
7 TX7MASK 0-1
6 TX6MASK 0-1
5 TX5MASK 0-1
4 TX4MASK 0-1
3 TX3MASK 0-1
2 TX2MASK 0-1
1 TX1MASK 0-1
0 TX0MASK 0-1
92
EMAC/MDIO Module
Reserved
Reserved
5 4
TX5MASK TX4MASK
R/W1S-0 R/W1S-0
Description
Reserved
Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
© 2011, Texas Instruments Incorporated
Figure 47
R-0
R-0
3 2
TX3MASK TX2MASK
R/W1S-0 R/W1S-0
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and described in
16
8
1 0
TX1MASK TX0MASK
R/W1S-0 R/W1S-0
SPRUFL5B – April 2011
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