8.24 Isochronous Transmit Interrupt Mask Register
The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel
basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit
interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt
event register bits detailed in Table 8−17.
Bit
31
30
29
Name
Type
R
R
R
Default
0
0
0
Bit
15
14
13
Name
Type
R
R
R
Default
0
0
0
Register:
Isochronous transmit interrupt mask
Offset:
98h
9Ch
Type:
Read/Set/Clear, Read-only
Default:
0000 00XXh
28
27
26
25
Isochronous transmit interrupt mask
R
R
R
R
0
0
0
0
12
11
10
9
Isochronous transmit interrupt mask
R
R
R
R
0
0
0
0
set register
clear register
24
23
22
21
R
R
R
R
0
0
0
0
8
7
6
5
R
RSC
RSC
RSC
RSC
0
X
X
X
20
19
18
17
R
R
R
R
0
0
0
0
4
3
2
1
RSC
RSC
RSC
RSC
X
X
X
X
16
R
0
0
X
8−23